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Simulators >> Circuit Simulators >> MIM Capacitor and PAD Layout problem of UMC90nm CMOS
https://designers-guide.org/forum/YaBB.pl?num=1241631415

Message started by Jack on May 6^th, 2009, 10:36am

Title: MIM Capacitor and PAD Layout problem of UMC90nm CMOS
Post by Jack on May 6^th, 2009, 10:36am

Dear All,

I am drawing the layout using UMC90nm CMOS library. When I connect the MIM capacitors and PAD, It always has the DRC warnings.

The warning for the PAD is: a staggered pad should have the minimum width of the pad window (PASV_RDL) 52um. But actually I set the pad in-line, not staggered. I don't know why this warning cannot be solved however I change the position of the pad.

The warning for MIM capacitors is: All Cu-Metal layers are recommended to avoid touching MIMBP (MIM bottom plate).

I have been troubled by these two warnings for several days. But I cannot solve them.

Does anybody knows how to connect the PAD and MIM Capacitor with the metal line in UMC90nm CMOS? Please help me!

Thank you very much!

By the way, I have read all of the information in the technology file, but I don't think the file describe it well. So I want get some help from the experienced designers.

Jack