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Design Languages >> Verilog-AMS >> Verilog-A/MS
https://designers-guide.org/forum/YaBB.pl?num=1241900578

Message started by Dracon on May 9^th, 2009, 1:22pm

Title: Verilog-A/MS
Post by Dracon on May 9^th, 2009, 1:22pm

Does anybody have any simulator summary that supports Verilog-A and Verilog-AMS from diffrent companies and their advantages and disadvantages?

thx

Title: Re: Verilog-A/MS
Post by jbdavid on May 11^th, 2009, 1:23pm

only rudimentary: - and from my point of view

Cadence: AMSD - my workhorse for nearly 10years - they even support fast transistor sims
Dolphin Smash: low cost, has an evaluation version I think.
GNUCAP: free - but not full featured yet
Synopsys VCS-Nanosim: Not integrated into ADE, might not support true mixed signal model styles - built on a premier Fast Spice.
Mentor - EldoAMS - VHDL centric model
others?

Title: Re: Verilog-A/MS
Post by pancho_hideboo on May 11^th, 2009, 8:40pm

jbdavid wrote on May 11^th, 2009, 1:23pm:

Synopsys VCS-Nanosim: Not integrated into ADE, might not support true mixed signal model styles - built on a premier Fast Spice.

What do you mean by "might not support true mixed signal model styles" ?

Title: Re: Verilog-A/MS
Post by jbdavid on May 14^th, 2009, 6:34pm

What I mean by might not support true mixed signal model styles
is that I've not heard satisfactory answers to my questions about using always and analog blocks in the same model.
-- What I've heard they support is Verilog + Verilog-A
Which I don't consider satisfactory for my normal purposes..

It hasn't helped that SNPS laid off my main contact with those guys..

Title: Re: Verilog-A/MS
Post by pancho_hideboo on May 16^th, 2009, 3:56am

jbdavid wrote on May 14^th, 2009, 6:34pm:

I've not heard satisfactory answers to my questions about using always and analog blocks in the same model.

There is no such limitation.

jbdavid wrote on May 14^th, 2009, 6:34pm:

-- What I've heard they support is Verilog + Verilog-A

"Nanosim+VCS" supports full Verilog-AMS surely.

However I feel an implemenation of IE(Interface Element) is poor.

Title: Re: Verilog-A/MS
Post by jbdavid on Jun 1^st, 2009, 6:00pm

I've not heard this from an SNPS AE,
nor have I seen this.
so you may think "surely" but I'm from Missouri. Show Me.

Jonathan

Title: Re: Verilog-A/MS
Post by pancho_hideboo on Jun 8^th, 2009, 1:31am

jbdavid wrote on Jun 1^st, 2009, 6:00pm:

I've not heard this from an SNPS AE,
nor have I seen this.

Verilog-AMS has been supported since "VCS2006.06SP2".

Title: Re: Verilog-A/MS
Post by pancho_hideboo on Jun 8^th, 2009, 1:35am

Unsupported Features.

Title: Re: Verilog-A/MS
Post by jbdavid on Jun 23^rd, 2009, 2:04pm

the $dist functions are quite useful..
as is Detailed discipline resolution.. Which, when I run anything in analog mode is what I use..
Other than that its a good start..
and I might be able to get it to work in some cases.
But I would probably chafe at the restrictions..
Thanks for the info..

Title: Re: Verilog-A/MS
Post by pancho_hideboo on Jun 24^th, 2009, 4:44am

There is an issue about current "Nanosim+VCS".

Current "Nanosim+VCS" does not have mixed-signal data format such as "sst2".

So we have to treat two files, VCD and FSDB.
CosmosScope can handle these.
http://www.designers-guide.org/Forum/YaBB.pl?num=1231424371/1#1