The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> minimal threshol value
https://designers-guide.org/forum/YaBB.pl?num=1242160958

Message started by analogue_guy on May 12^th, 2009, 1:42pm

Title: minimal threshol value
Post by analogue_guy on May 12^th, 2009, 1:42pm

Hi all,

Can anyone collect the guidelines how to size a transistor in order to have the minimum threshold value?

like effect of the gate length, effect of the number of foldings...

cheers

Title: Re: minimal threshol value
Post by raja.cedt on May 12^th, 2009, 7:31pm

hi,
i guess it wont depend on the no of foldings but according to short channel effects vth will decrease with length (but if you have pocket holo's in your transistor,at very small length because of reverse short channel effect vth will increase with decrease in length)

Thanks,
Rajasekhar.

Title: Re: minimal threshol value
Post by Berti on May 12^th, 2009, 10:36pm

Quote:

i guess it wont depend on the no of foldings

It depends on the technology, but due to STI induced stress the threshold voltage will depend on the number of fingers (distance of gate to STI). The vt of a PMOS will be lower in the presence of STI stress. For NMOS it is the other way.

Cheers