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Design >> Analog Design >> Problem designing a simple common source amp
https://designers-guide.org/forum/YaBB.pl?num=1242645728

Message started by kidman on May 18^th, 2009, 4:21am

Title: Problem designing a simple common source amp
Post by kidman on May 18^th, 2009, 4:21am

I have attached a PDF file explaining everything because I show lots of plots. Please download it and see. I think anyone here can know the problem easily because its just a simple common source. Thanks

Title: Re: Problem designing a simple common source amp
Post by wave on May 18^th, 2009, 9:26am

Re-read you problem. It asks for output of 0.3-0.9V, not input range.
That is the large signal range. Input should be small signal.
Vo/gain = 0.6/30 = 20mV, pretty small.

You need to pick a Vgate, so that Vgs > Vth, for all 20mV range.

Wave

Title: Re: Problem designing a simple common source amp
Post by ndnger on May 19^th, 2009, 12:54am

Hey Kidman,

You haven't taken care of the DC biasing of your circuit. When you use an ideal current source on top of the NMOS, it forces the NMOS current to equal the DC current at all input levels. Hence for low values of Vin, your Vout shoots up to 20 V !! The device is operating in subthreshold region with a large Vds to support the ideal current bias value. Your design has a gain of 30 under ideal DC current bias for a particular value of Vgs and Vds ~ 0.2V.

When you use the PMOS load, you get the inverter like characteristics and Vout Vs Vin is not the same as what you got with ideal current bias. ro is a function of Vds and when your amplifier is in high gain region Vds is > 0.2V and hence ro is large now. What you need to do your design with a PMOS load as it affects your DC characteristics and also gain and BW.