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Design Languages >> Verilog-AMS >> Interpreting input logic busses as signed integers
https://designers-guide.org/forum/YaBB.pl?num=1242651957

Message started by Alexander Eßwein on May 18^th, 2009, 6:05am

Title: Interpreting input logic busses as signed integers
Post by Alexander Eßwein on May 18^th, 2009, 6:05am

Hello,

I am modelling the behaviour of a DCO after Staszewski in Verilog-AMS.

As there are no integer type ports in Verilog, i have a bus of logic ports that i use to read the digital control word from.

I would like this port to behave like a signed integer input, but it only interprets the input as unsigned. How can I make the input behave like it is a signed integer port?

An example code of the DCO is attached.

Title: Re: Interpreting input logic busses as signed integers
Post by Peruzzi on May 20^th, 2009, 12:38pm

Hello Alexander,
I am guessing that the Staszewski case you are following is one in which he used VHDL (non AMS) and thus was limited to integer and real ports to carry analog information.

Since you are using Verilog-AMS you don't have that limitation. You can use wreal signals and ports to carry your signed integers.

Hope this helps.

Bob P.
www.RPeruzzi.com

Title: Re: Interpreting input logic busses as signed integers
Post by jbdavid on Jun 1^st, 2009, 5:53pm

use the keyword "signed" on the wire where you declare it

from 1364-2005 paragraph 12.3.3:

Code:

input_declaration ::=
input [ net_type ] [ signed ] [ range ] list_of_port_identifiers

if you used the signed keyword, the resulting integer will be treated just like a signed register.

Code:

`timescale 1ns / 1ps
`include "disciplines.vams"

module dco_1 (out, ps, ns, DCO_CONTROL);
parameter real f0 = 100k from (0:inf); // center frequency (Hz)
parameter real kvco = 10k; // gain (Hz/V)
parameter real DCO_QUANT = 100p; // period deviation per digital step
input signed [7:0] DCO_CONTROL; // digital control word
input ps, ns;
output out;
electrical ps, ns;
logic [7:0] DCO_CONTROL;
reg out;
logic out;
real vin;
real din;

initial out = 0;

always begin
vin = V(ps, ns);
din = DCO_CONTROL * DCO_QUANT;
#((0.5e9 / (f0 + kvco * vin)) - ( din / 2))
out = ~out;
end
endmodule

Title: Re: Interpreting input logic busses as signed integers
Post by Alexander Eßwein on Jun 2^nd, 2009, 4:04am

Thank you Guys, that very much did the trick!