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Simulators >> Circuit Simulators >> startup circuit..initial conditions..trans sim
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Message started by somisetty on May 19^th, 2009, 7:53am

Title: startup circuit..initial conditions..trans sim
Post by somisetty on May 19^th, 2009, 7:53am

hi,

would pls let me know what need to be the initial condition for the nodes to test the startup circuit transient sim?

FYI:pls find the circuit attached with nodes labeled...

Thanks a lot....

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 19^th, 2009, 8:17am

hi somisetty,
i didn't understand your question because if you don't have any start up circuit and you want to check weather your ckt is working or not then initializes one of the node to some intermediate potential..

But you already have start up circuit,so during starting v- will be at zero potential so some current will flow through Q2 hence ckt will start so don't think this need any internalization.

Thanks,
Rajasekhar.

Title: Re: startup circuit..initial conditions..trans sim
Post by salty on May 19^th, 2009, 9:12am

You could ramp your supply, that should allow you to see the start-up ckt. working.

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 19^th, 2009, 9:56pm

Thanks for the reply...

i just like to elaborate my problem....

As you know the BGR has two stable operating points: One in which no current is flowing through the circuit which is the unwanted condition and the second is the desired operation .

To avoid the unwanted operating point we use a startup circuit.

I wanted to simulate the BGR without startup circuit by setting initial conditions to the nodes and see the unwanted condition…(so I did the below sim’s in DC and Tran)

1) I set the initial conditions of the nodes Vc1 to VDD and V-/V+ to zero, performed the DC simulation and saw all the transistors went into cut off (i.e which is the undesirable condition)

2) I set the initial conditions of the nodes Vc1 to VDD and V-/V+ and VDD ramping (ramp is 15u),performed the tran sim and, I see the BGR is not failing but building up the voltage to 1.2V.

My doubt is why the BGR didn’t fail in the tran sim.am I doing the tran sim correctly?

What I wanted to do next once I see the BGR failing in tran sim, I will connect the startup circuit and I should see the BGR building up the voltage (i.e., the startup is functioning)

Thanks again...

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 19^th, 2009, 10:16pm

hi,
in 2nd case you are initializing nodes to other than 0 volts,then it will start and same thing happened in your sim also...No doubt your BGR working..connect startup ckt and check..i think it will work.

thanks,
rajasekhar.

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 20^th, 2009, 3:11am

Thanks for the reply..

its my mistake..

2) I set the initial conditions of the nodes Vc1 to VDD , V-/V+ to zero and VDD ramping (ramp is 15u),performed the tran sim and, I see the BGR is not failing but building up the voltage to 1.2V.

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 20^th, 2009, 4:16am

hi
i think you are wasting some power in startup unnecessarily,you can remove Ms1,Ms3.

Thanks,
rajasekhar.

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 20^th, 2009, 7:28pm

okie...Thanku

i will try removing them and check it...

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 25^th, 2009, 9:59pm

hi..

i removed Ms1 and Ms3 and connected the circuit using Ms2.

As i connected only Ms2,the MS2 was in linear and pumping current to V- node in normal operation .So i cascoded the same to disable the Ms2 .I see the startup action happening.But the startup is slow,i mean there is very less difference between the startup time of the BGR with startup and without startup . Pls find the circuit attached...

I read that this kind of architecture degrades PSRR,i am not sure...

The use of startup circuit is to avoid the undesirable operating point in the circuit.Is it that startup circuit also helps in bringing up the bandgap voltage quicker compared to without startup?

Thanks

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 26^th, 2009, 12:24am

hi,
how this startup ckt will effect psrr.Actually the basic property of the startup ckt is it should n't affect its normal operation, moreover settling time of bandgap independent of startup because once a startup ckt introduce disturbance, thats it BGR will take care remaining things(because while starting BGR is +ve feedback ckt so very fast).Why dont you use very simple startup which you can in razaavi?

Thanks,
Rajsekhar.

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 26^th, 2009, 2:46am

hi,

Thanks rajsekhar...

i will check in razzavi (for the simple startup circuit)...

Somisetty

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 27^th, 2009, 12:10am

hi,
how did you noticed that your startup is effecting settling time?
and use the attached startup,it wont give any problem.

Thanks,
Rajasekhar.

Title: Re: startup circuit..initial conditions..trans sim
Post by subgold on May 27^th, 2009, 2:05am

raja.cedt wrote on May 27^th, 2009, 12:10am:

hi,
how did you noticed that your startup is effecting settling time?
and use the attached startup,it wont give any problem.

Thanks,
Rajasekhar.

hello raja,

you suggested somisetty to remove two transistors to save power for the normal operation. but doesn't this circuit has the same power wasting problem?

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 27^th, 2009, 2:33am

no it wont waste power because top pmos has very small aspect ratio (typically 1/20),or if you have any power budget allocate small fraction of power to startup ckt and you can play with that pmos aspect ratio.

Thanks,
Rajasekhar.

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 27^th, 2009, 9:11pm

hi,
how did you noticed that your startup is effecting settling time?
and use the attached startup,it wont give any problem.

Thanks,
Rajasekhar.

Hi Rajasekahar,

i did two types of simulation for seeing the settling time in different corners...

1)Did tran (VDD ramp) without initial conditions for BGR with startup and without startup.

2) Did tran (VDD ramp) with initial conditions for BGR with startup and
without startup.(initial condition Vc1 to VDD)

In 1st case i see the settling time for BGR with startup is late compared to without startup...(the difference is less..but late with startup..)

In the 2nd case i see the settling time for BGR with startup is early compared to without startup...

iam doing the startup u suggested..will let u know the results...

Thanks again
Somisetty

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 27^th, 2009, 9:31pm

hi,
seems like some mistake is there while confirm about settling time.Do the following
1.rum .tran without startup ckt but initialize some node
2.run .tran with startup and this time don't initialize any node.

thanks,
rajasekhar

Title: Re: startup circuit..initial conditions..trans sim
Post by somisetty on May 27^th, 2009, 11:26pm

Hi Rajasekhar,

Thanks for the reply...

you mean to say that i need to compare the settling time's of 1 and 2 ?
1.run .tran without startup ckt but initialize some node
2.run .tran with startup and this time don't initialize any node.

Thanks,
SOmisetty

Title: Re: startup circuit..initial conditions..trans sim
Post by raja.cedt on May 28^th, 2009, 1:18am

yes..you do those simulations and see is these discrepancy of operating point along with all dynamics between them.

Thanks,
Rajasekhar.