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Simulators >> Circuit Simulators >> switched capacitor in cadence
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Message started by Mahyar on May 22^nd, 2009, 3:34pm

Title: switched capacitor in cadence
Post by Mahyar on May 22^nd, 2009, 3:34pm

Hi
I am trying to design a switched capacitor sampling system in virtuoso schematic editor. But I don't know how to:
1- Generate non-overlapping clocks.
2- How to model the switches? should I use like nfet or there are special switches?

Thank you,
M

Title: Re: switched capacitor in cadence
Post by thechopper on May 22^nd, 2009, 5:26pm

A simple approach using ideal components:

1) For non-overlapping clocks just define a variable for the clock period - say Tck. The use two vpulse sources where the first one has a period Tck and a duty cycle of 49.5%. The second source will have the same period and duty cycle but a delay equal to 0.5Tck.
In this way you can change Tck and keep the non-overlapping feature of your clocks.
2) there is an ideal switch in the analogLib simply called "switch". It is voltage controlled and therefore you need to set the Vth high and low and also you can set the resistanc in ON state for such switch.

With these two ideal components you could start designing your SC system.

Regards
Tosei