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Design >> Analog Design >> voltage buffer design
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Message started by subgold on May 26^th, 2009, 2:19am

Title: voltage buffer design
Post by subgold on May 26^th, 2009, 2:19am

Does anybody have some ideas on how to design a voltage buffer which can cover VSS? the input range is from VSS to VDD/2.

of course, some sort of level shifter based structures can do the job. but are there any structures which have no level shifting? Due to the application, i want the buffer only to change the impedance, but not the voltage level.

thanks.

Title: Re: voltage buffer design
Post by raja.cedt on May 26^th, 2009, 2:28am

hi ,
what do you mean by 'i want the buffer only to change the impedance, but not the voltage level'. I understood that you need a buffer which has to work from vss to vdd/2.For this one i think pmos based op amp will work.

Thanks,
Rajasekhar.

Title: Re: voltage buffer design
Post by subgold on May 26^th, 2009, 2:59am

raja.cedt wrote on May 26^th, 2009, 2:28am:

sorry i didn't formulate the question very clearly. the following stage of the buffer has a quite low input impedance, so i use the buffer only as a driver, but i want the dc level of the buffer input and output to be the same.

how will the pmos opamp work? i assume you mean a noninverting configuration of the opamp. that means both inputs and output of the opamp have to go down to VSS. but the output level cannot be lower than one Vdsat above VSS.

Title: Re: voltage buffer design
Post by solidstate on May 27^th, 2009, 5:56am

The only way to drive really down to VSS while still having gain in your buffer is to operate the buffer from a supply lower than VSS... (think charge pumps).

What is driving the buffer in the first place? Is your signal source going all the way down to VSS? Maybe you can apply a DC shift there, to ease the buffer design...

Title: Re: voltage buffer design
Post by subgold on May 27^th, 2009, 10:06am

solidstate wrote on May 27^th, 2009, 5:56am:

the signal source is really going down to vss, and a dc shift is also sort of buffer.

i think i asked a stupid question in the very first place. 'such circuit is impossible' is also a good answer to know :)

Title: Re: voltage buffer design
Post by solidstate on May 27^th, 2009, 10:23am

Well, the circuit you had in mind is probably 'impossible', but solving your problem certainly is not. Maybe some more info about the signal source and the application could help us help you?

Title: Re: voltage buffer design
Post by Berti on May 27^th, 2009, 11:50pm

Just an idea:
By having a resistive load you could operate the buffer lower than vdsat.

Cheers

Title: Re: voltage buffer design
Post by raja.cedt on May 28^th, 2009, 12:19am

hi Berti,
could you please explain how resistive load decrease vdsat.
Thanks,
Rajasekhar.

Title: Re: voltage buffer design
Post by Berti on May 28^th, 2009, 2:07am

Consider just a simple differential pair with PMOS input transistors and resistors on the load side (or even only a source-follower) in unity-gain feedback configuration. This circuit should still work at relatively low input voltages.

Regards