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Design >> Analog Design >> DRC problem with IBM PDK
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Message started by newbie designer on May 28^th, 2009, 7:28pm

Title: DRC problem with IBM PDK
Post by newbie designer on May 28^th, 2009, 7:28pm

Hello,

I have access to the IBM PDKs for both 65nm (cmos10lpe) and 45nm (soi120S). I wanted to test the PDK and the DRC tool so I made a layout containing just one nmos and ran DRC on it. To my surprise, I got DRC errors for the IBM PDK nmos cell using the IBM PDK DRC runset. Shouldn't the cell provided in the PDK be error-free?

Another question is specific to the 45nm PDK (soi120S): on the nmos and pmos cell, there are poly layer strips (pc) that are close but separated from source and drain. What purpose do these poly layer strips serve?

Finally, I am quite new to layout design with PDks. In fact, I have only used Cadence gpdk and TSMC 0.25um PDK before; both are much easier to use than the IBM 65nm and 45nm PDK that I have to use for my project. Does anyone know if there is a good layout tutorial that uses IBM PDKs, or if anyone is expert with these PDKs, may I ask you more related question privately?

Thanks anyone for their help in advance!!

Title: Re: DRC problem with IBM PDK
Post by oermens on May 28^th, 2009, 8:36pm

You dont like the IBM PDKs? I'm using cmos8rf at my university and everyone thinks its great compared to what we previously used (TSMC .18). Anyways...

More info would be helpful. What DRC are you using (Assura, Calibre, other)? What DRC errors are you encountering? It could be something related to your setup and not the Pcells.

The documentation we got for cmos8rf covers a lot of layout and DRC/LVS/extraction topics. Ask MOSIS (if you're a customer) to provide you with any IBM training documents that don't come packaged with the kit (i.e. those that are in /IBM_PDK/<tech>/<rel>/doc and /IBM_PDK/<tech>/<rel>/cdslib/doc). Try asking on http://tech.groups.yahoo.com/group/MOSIS_Users_Group/ to interact with other IBM PDK users.

Schematic-driven layout makes life a lot easier. The PDK comes with pcells (schematic and layout views) for bondpads and esd so you can include these from the schematic level, then generate the layout pcells in virtuoso layout xl and do the placement and routing.

Title: Re: DRC problem with IBM PDK
Post by newbie designer on Jun 12^th, 2009, 12:49pm

Hi oermens,

Thanks fo your response. Sorry I know it has been a while since I last posted. I have finally solved the problem. What happend was that when I export my layout using Stream, I did not apply the mapping file. I think withing proper mapping, DRC tools apply wrong rules to wrong layers. In one case I was getting an error such as "width == length == 0.1um" for poly. It looks like if I don't apply the mapping file, DRC tool interpret poly as contact in this case. After I apply the mapping everything works out perfectly.

Thanks again