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Simulators >> AMS Simulators >> AMS-Spectre PLL Simulation Problem
https://designers-guide.org/forum/YaBB.pl?num=1243825430

Message started by rajat on May 31^st, 2009, 8:03pm

Title: AMS-Spectre PLL Simulation Problem
Post by rajat on May 31^st, 2009, 8:03pm

Hi Guys
I have run into a weird problem while trying to simulate a voltage domain PLL using AMS spectre. The PLL model i.e. the Osc, VCo and Pfd/cp are essentially the same as described in Ken's paper. The additions being a fractional accumulator(verilog) and interface connect modules E2L_0 & L2E_0 from the connect_lib library. I explicitly instantiate the connect modules in my model and thus leave the 'connect rules' field empty while setting up my simulation in AMS. The output from the L2E module which represents the carry out from the accumulator is not connected to the VCO but is grounded using a resistor, as I wanted to test its output first. Here are the module interconnections :

`timescale 100ps/10ps
initial begin
rst_n = 0;
#200000 rst_n = 1; //200000 * 100ps = 20 us
end

osc #(.freq(25M),.ratio(1), .Vlo(0), .Vhi(1), .accJitter(0),.syncJitter(0))
ref_osc (.out(ref_clk));

pfd_cp #(.Iout(200u), .dir(1), .vth(0.5), .tt(1n), .ttol(0.5n))
PFD_CP (.out(err), .ref(ref_clk), .vco(vco_clk));

cap #(.c(786p)) C1(err, err2);

res #(.r(3.21k)) R1(err2, gnd);

cap #(.c(86.8p)) C2(err, gnd);

vco #(.Vmin(0), .Vmax(2.5), .Fmin(5175M), .Fmax(6475M),
.ratio(229), .Vlo(0), .Vhi(1), .jitter(3.41f), .outStart(1m))
vco_osc ( .in(err), .out(vco_clk) );

E2L #( .vsup(1), .vthi(0.5), .vtlo(0.5) )
E2L_0 ( .Ain(vco_clk), .Dout(clk_dig) );

accum accum_0 ( .clk(clk_dig), .rst_n(rst_n), .f(f_in),.f2s(f2s_in),
.accum_in(accum_in), .carry(carry), .accum_out(accum_out));

L2E #( .vsup(1), .vhi(1), .vlo(0), tr(1n), .rout(200) )
L2E_0 ( .Aout(el_carry), .Din(carry) );

res #(.r(1M)) R3(el_carry, gnd);

The expected operation of the PLL which is essentially an Integer-N PLL in the case :
1.) The rst_n is held low and the digital accumulator is inactive.
( PLL works perfectly well as expected.)
2.) The digital accumulator is now enabled and the carry out signal el_carry is grounded using a resistor. ( The err signal behaves strange after a while !! )

Why does this happen ?? The err signal seems to be influenced by something.

Would really appreciate some pointers.
Thanks

PS : Setting for the analog simulation are SPECTRE defaults.