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Design >> RF Design >> Duty cycle of reference/divider clocks in PLL
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Message started by boa on Jun 3^rd, 2009, 5:08am

Title: Duty cycle of reference/divider clocks in PLL
Post by boa on Jun 3^rd, 2009, 5:08am

Hi all,

From what I see in different PLL designs, typical N-divider output clock (as well as reference clock in case it's divided in R counter from quarz) has a duty cycle of approx. 20-25%. What's the idea behind it?

The only thing that comes to my mind is that the spectrum differences when compared to 50% duty cycle, maybe this helps against unwanted mixing, i.e. via substrate leakage etc. But when I look at FFTs of clocks with 20% and 50% dyty cycles, that does not look so straightforward to me..

Title: Re: Duty cycle of reference/divider clocks in PLL
Post by loose-electron on Jun 3^rd, 2009, 6:56am

I don't see any good reason to do anything but 50% duty cycle, and thats what all of my PLL's have used.

Smaller duty cycle will raise some of the higher frequency harmonics, and thats only going to make noise/coupling issues worse.

Title: Re: Duty cycle of reference/divider clocks in PLL
Post by salty on Jun 5^th, 2009, 3:55pm

Usually 50% duty cycle is attained by wide synchronous counters. Faster counters can be obtained by ripple counters. Since the PFD (In charge pump plls) usually work on the edges, the duty cycle is not as important.

Title: Re: Duty cycle of reference/divider clocks in PLL
Post by boa on Jun 19^th, 2009, 4:30am

Thanks!
I agree, I also could not find any specific reason for anything but 50% duty cycle.

Title: Re: Duty cycle of reference/divider clocks in PLL
Post by oermens on Feb 4^th, 2010, 7:49am

Sorry to revive such an old topic but I am wondering about this myself. I am working with verilog-a models logic blocks (from cadence IC bmsLib) before going to circuit level design, and I noticed that the output of an integer-n divider is very short pulses but they have the correct frequency. What are typical methods to obtain 50% duty cycle from the divider? I was thinking to design the divider to output 2f_ref then feed that into a Master-Slave divide by 2 to get f_ref with 50% duty cycle. Are there other/better ways?

Title: Re: Duty cycle of reference/divider clocks in PLL
Post by loose-electron on Feb 4^th, 2010, 6:20pm

divide by 2 is the most common - always use that in PLL that gets used as a mixer downconvert

going off just one edge in other devices is still good there will be some subtle duty cycle variance because of the difference in Trise vs. Tfall