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Other CAD Tools >> Physical Verification, Extraction and Analysis >> Cadence cell-design tutorial question
https://designers-guide.org/forum/YaBB.pl?num=1244157823

Message started by joel on Jun 4^th, 2009, 4:23pm

Title: Cadence cell-design tutorial question
Post by joel on Jun 4^th, 2009, 4:23pm

Hi All,
I'm trying to work through the cell-design tutorial bundled with Cadence Virtuoso. I'm sure this is kindergarden stuff for most of you! But I'm stuck at the LVS step.

Netlisting the schematic works fine.
Creating the extracted view of the layout seems to work fine.
Netlisting the extracted view fails.

From the extracted-view window, I bring up the verify/lvs form.
I click the create-netlist for extracted-view, give it the appropriate names, set priority to 20 as instructed and click 'Run'.

Up comes the banner that says "Job Failed, you looser!".
From Info/log I see the following error report, one for each transistor in the layout:

Cannot find switch master cell for instance +I3 in cellView (mux2 extracted) from viewlist 'auLvs extracted schematic' in library 'master'

It does this even if I use the extracted layout in the master library (supplied by Cadence), rather than the tutorial library (generated by me).

Any idea what's going wrong? What's a switch master cell? What's an auLvs view?

thnx, /jd

Title: Re: Cadence cell-design tutorial question
Post by oermens on Jun 4^th, 2009, 5:41pm

joel wrote on Jun 4^th, 2009, 4:23pm:

Up comes the banner that says "Job Failed, you looser!".

Sorry I don't have anything to contribute, but does it actually say that? What tutorial is this exactly?

Title: Re: Cadence cell-design tutorial question
Post by joel on Jun 4^th, 2009, 6:04pm

Nah, it's not that directly insulting. It just insidiously makes my afternoon miserable.

This is the tutorial that's bundled with Cadence Virtuoso. If you bring up cdsDoc, expand the 'Virtuoso Layout Editor' chapter, there is a 'Cell Design Tutorial'. You'll find it in $INSTALLDIR/dfII/samples/tutorials/le/cell_design .

I find that the layout uses various pCells for transistors, some of which have auLvs view and some not. In the extracted view, all transistors are view 'ivpcell' of cell pfet or nfet as appropriate, from library sample. sample/pfet and sample/nfet do not have auLvs views, presumably what the netlister is complaining about.

It just seems amazing to me that the tutorial has a bug, straight from Cadence. So I must be doing something wrong.

Title: Re: Cadence cell-design tutorial question
Post by joel on Jun 4^th, 2009, 6:54pm

At a glance, the Diva rule file looks reasonable. This is what is in my LVS run directory:

(lvsRules
procedure((fetCompare lay sch)
prog(nil
if(((lay->l) && (sch->l))
if((abs(((lay->l) - (sch->l))) > (0.1 * (sch->l)))
return(t)
)
)
if(((lay->w) && (sch->w))
if((abs(((lay->w) - (sch->w))) > (0.1 * (sch->w)))
return(t)
)
)
return(nil)
)
)
(compareDeviceProperty "nfet" fetCompare)
(compareDeviceProperty "pfet" fetCompare)
)

I tried copying auLvs views into all the various versions of n & p transistor cells in my library. But I get the same error message.

The extracted view looks good as far as I can tell. There's a little transistor schematic symbol with the extracted width & length at the top of each layout device, and the fly-lines marking connectivity look about right.

The schematic netlists fine, so I don't seem to be having a license problem.

But I just can't get an extracted netlist out of the extracted layout. All the pop-up forms look just like the pictures in the tutorial. Could it be that something in my environment is interfering with netlisting?

Title: Re: Cadence cell-design tutorial question
Post by joel on Jun 4^th, 2009, 7:17pm

From the Diva Reference appendix C. Simulation and Environment Control, it seems to state that the 'switch cell' is defined by the lvsLayoutStopList, which should be "lvs" for doing LVS. It seems to be {auLvs extracted schematic} according to the error in my logfile. The reference says to control this, one types

lvsLayoutStopList = ' ( "lvs" )

When I enter that into the CIW, I get a syntax error.

At this rate, I think I'll switch to Mentor!

Title: Re: Cadence cell-design tutorial question
Post by joel on Jun 4^th, 2009, 7:28pm

OK, further reading larns me that the lvsLayoutStopList gets defined in the si.env file. So I try to set it to "lvs" as the manual states, even though the canned tutorial puts it as "auLvs". Of course this causes other errors...

Title: Re: Cadence cell-design tutorial question
Post by joel on Jun 5^th, 2009, 2:41pm

Looks like I'm not the only one. Here's two solutions that haven't worked for me:

http://www.edaboard.com/viewtopic.php?t=244320&highlight=cadence+cell+design+lvs+tutorial

http://www.edaboard.com/viewtopic.php?t=279979&highlight=cadence+cell+design+lvs+tutorial

Title: Re: Cadence cell-design tutorial question
Post by joel on Jun 11^th, 2009, 5:07pm

It turns out that at my site, when I type 'icfb' I'm actually invoking a wrapper. The wrapper would set CDS_Netlisting_Mode to Analog, overwriting whatever I might have otherwise set its value to be.

Modifying the wrapper to setenv CDS_Netlisting_Mode Digital allowed the LVS job to complete correctly.

By the way, setShellEnvVar("CDS_Netlisting_Mode=Digital") didn't help. For some reason this environment variable must be set before the icfb process is started, and can't be modified from within.

Good luck to all! /jd

Title: Re: Cadence cell-design tutorial question
Post by Andrew Beckett on Jul 10^th, 2009, 9:11am

Sorry for not replying sooner - I was busy for a few weeks (still am, really), and so didn't see this until now. I could have put you out of your misery sooner, otherwise...

Anyway, if you do change the environment variable in the CIW, you need to call cdsSetNetlistMode() to make sure it gets honoured:

Code:

setShellEnvVar("CDS_Netlisting_Mode=Digital")
cdsSetNetlistMode()

Best Regards,

Andrew.