The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> regulator question
https://designers-guide.org/forum/YaBB.pl?num=1244682116

Message started by jiesteve on Jun 10^th, 2009, 6:01pm

Title: regulator question
Post by jiesteve on Jun 10^th, 2009, 6:01pm

I'm building a regulator that will be used as a "controlled" pulldown for a bias node that needs to be pre-charged to VDD in some modes. This bias node needs to be brought down to a level Vbias, which is what the pulldown regulator is for. After it has been pulled down, the node is connected back to the bias generator.

The regulator is driving a purely capacitive load (NMOS gates). Do you guys see any problems with the scheme below? I've noted that it's possible, because of gate leakage and because there is no DC bias pullup for the node to drift down indefinitely, so the scheme will need to be timed so that leakage will not bring the node too low... Do you guys see any other issues?

Also, how do I go about performing AC analysis, since there is no DC path for the output node (top of cap)?

Title: Re: regulator question
Post by raja.cedt on Jun 11^th, 2009, 9:58am

hi jiesteve,
i didn't understand whats your problem, could you please explain why your using regulator, there are lot more regulator better than this? and why AC analysis is difficult here because you have path from output to ground through pmos.

Thanks,
rajasekhar.

Title: Re: regulator question
Post by jiesteve on Jun 11^th, 2009, 10:01am

I'm using the regulator to bring the top of cap to Vbias.

I think I need to somehow initialize the top of cap for DC bias calculation

Title: Re: regulator question
Post by salty on Jun 11^th, 2009, 12:08pm

One issue I see is when the switch is closed to Vdd, your PFET will
be turning on very hard and pulling a lot of current. Why can't
you put a switch to vbias and switch between vdd and vbias?

Title: Re: regulator question
Post by jiesteve on Jun 11^th, 2009, 1:24pm

When the switch is closed to VDD, the PFET and regulator are both turned OFF, so there is no DC current draw.

The bias generator is very high impedence, so I need the regulator to slew the cap back down to Vbias. The bias generator is not fast enough to slew the cap.