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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> phase margin in opamp circuit https://designers-guide.org/forum/YaBB.pl?num=1245076167 Message started by Evgenii on Jun 15th, 2009, 7:29am |
Title: phase margin in opamp circuit Post by Evgenii on Jun 15th, 2009, 7:29am Hi! :) Cmos opamp (two-stage, repeater) has output on I/O pad. Complex capacitance of this pad may has different amount, say, 10-15pF. How to disable auto-oscillations of this repeater w/o using big internal cap... :( Thanks! |
Title: Re: phase margin in opamp circuit Post by raja.cedt on Jun 15th, 2009, 10:34am hi, what do you mean by repeater, could be please give some more information regarding your opamp? Thanks, rajasekhar. |
Title: Re: phase margin in opamp circuit Post by Evgenii on Jun 16th, 2009, 1:30am Hi! Thanks for you reply! attached repeater1.pdf work ranges: VDD (3 V-6V) V_in (0.25 V - (VDD-2) V) R_load (3KOhm - 300kOhm) C_load (3-15pF) I mean need in some cascode schematic... :( Thanks. |
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