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Design Languages >> Verilog-AMS >> issue betwen blocking and no blocking
https://designers-guide.org/forum/YaBB.pl?num=1245080938

Message started by idriss on Jun 15^th, 2009, 8:48am

Title: issue betwen blocking and no blocking
Post by idriss on Jun 15^th, 2009, 8:48am

Hi Guys
I would like to know when I use this piece of code:

always @(c40 or d0b or c42 or d1b or c44 or d2b or c46 or d3b or pwrFault) q_latchp = #tdelay (!pwrFault) ? ~((c40 && d0b) || (c42 && d1b) || (c44 && d2b) || (c46 && d3b)):1'bx;

always @(c40 or d0n or c42 or d1n or c44 or d2n or c46 or d3n or pwrFault) q_latchn = #tdelay (!pwrFault) ? ~((c40 && d0n) || (c42 && d1n) || (c44 && d2n) || (c46 && d3n)):1'bx;

to model a CSVL kind of mux,I have the wrong datas but when I do no blocking code:

always @(c40 or d0b or c42 or d1b or c44 or d2b or c46 or d3b or pwrFault) q_latchp <= #tdelay (!pwrFault) ? ~((c40 && d0b) || (c42 && d1b) || (c44 && d2b) || (c46 && d3b)):1'bx;

always @(c40 or d0n or c42 or d1n or c44 or d2n or c46 or d3n or pwrFault) q_latchn <= #tdelay (!pwrFault) ? ~((c40 && d0n) || (c42 && d1n) || (c44 && d2n) || (c46 && d3n)):1'bx;

I have correct outputs
Can someone explain me the differences and where the issue comes from.

Thank you very much
idris