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Design >> Analog Design >> a question about PNoise simulation
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Message started by uu@uk on Jun 16^th, 2009, 2:39pm

Title: a question about PNoise simulation
Post by uu@uk on Jun 16^th, 2009, 2:39pm

Hi all,

I am running Pnoise simulations for a differential buffer driven by a clock signal. The first I did is 1GHz(beat frequency in PSS) and I also ran another 125MHz(beat frequency in PSS). I got the almost the same phase noise plot(they are relative to 1GHz and 125MHz carrier frequency seperateley).

However, the phase noise formula is 10log(2KT*f0^2/(P*delf^2)) (refer to Hajimiri's paper). According to the above formula(f0 is carrier frequency), is it phase noise at a small carrier frequency could be better? Anyone could explain it? Thanks a lot.

Title: Re: a question about PNoise simulation
Post by pancho_hideboo on Jun 16^th, 2009, 4:54pm

uu@uk wrote on Jun 16^th, 2009, 2:39pm:

However, the phase noise formula is 10log(2KT*f0^2/(P*delf^2)) (refer to Hajimiri's paper).
According to the above formula(f0 is carrier frequency), is it phase noise at a small carrier frequency could be better?

This assumed resonator around f0.
Derive this formula by yourself.
Is there resonator in your circuits ?

Title: Re: a question about PNoise simulation
Post by uu@uk on Jun 16^th, 2009, 5:17pm

Hi,

NO! there is no resonator in my circuit. It is just a differential in and differential out current steering amplifier. It is a driven circuit(driven by rail to rail clk signal) but not autonomous cuitcuit. So I suspect the phase noise formula I wrote down(it is for oscillator) is applicable in this case.

Title: Re: a question about PNoise simulation
Post by pancho_hideboo on Jun 16^th, 2009, 5:25pm

uu@uk wrote on Jun 16^th, 2009, 5:17pm:

NO! there is no resonator in my circuit.

I know it.
What I want to say is "Don't use formula blindly".

uu@uk wrote on Jun 16^th, 2009, 5:17pm:

So I suspect the phase noise formula I wrote down(it is for oscillator) is applicable in this case.

How to write down ?
Show me your derivation process.

Title: Re: a question about PNoise simulation
Post by uu@uk on Jun 16^th, 2009, 7:26pm

Hi,

you are right. The f0 there is coming out because of the L and C oscillating freqeuncy. It does not make sense to use that formula to predict the driven circuit. I made a mistake there.

This is the current steering circuit. So the current charge the capacitor at the output is the same even in those two frequency input clock signal. Then I think the edge rate at the crossing point would not be different(I also run the simulation to look at that). Then the rms jitter(hence phase noise) should not be too much different even at 125MHz and 1GHz.

Thanks for pointing out the mistake.

Title: Re: a question about PNoise simulation
Post by pancho_hideboo on Jun 16^th, 2009, 8:27pm

uu@uk wrote on Jun 16^th, 2009, 7:26pm:

The f0 there is coming out because of the L and C oscillating freqeuncy.

It seems you don't still understand this formula correctly.
In this formula, an important factor is bandwidth of loaded resonator which is determined by value of f0.
Value of f0 itself is not important.