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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> latch comparator problem https://designers-guide.org/forum/YaBB.pl?num=1245280451 Message started by salma shabayek on Jun 17th, 2009, 4:13pm |
Title: latch comparator problem Post by salma shabayek on Jun 17th, 2009, 4:13pm i am trying to simulate a fully differential dynamic comparator in 0.13um process, vdd=1.2v, when the threshold is zero i have only one error when the ramp is falling below the zero( threshold) attached is my simulation ; the ramp is the positive input,the purple line is the clock and the blue line is the positive output the clock switching the pmos transistors has a delay of 200ps from the external clocks of the system i also want to know if i want to adjust a threshold , what to do ? i know we add 2 transistors with vthreshold=(Wref/Win)*Vref but I've read thats a theoratical rule...does anyone know whats the practical?? |
Title: Re: latch comparator problem Post by salma shabayek on Jun 17th, 2009, 4:17pm and here is the schematic |
Title: Re: latch comparator problem Post by ywguo on Jun 18th, 2009, 2:37am Hi, M15 and M16 are not symmetry in the schematic. Probably something is wrong. Yawei |
Title: Re: latch comparator problem Post by nobody on Jun 18th, 2009, 3:06am Do you add M15, M16 to cancel the miller effect ? |
Title: Re: latch comparator problem Post by salma shabayek on Jun 18th, 2009, 6:05am No to cancel the kick back noise |
Title: Re: latch comparator problem Post by raja.cedt on Jun 18th, 2009, 7:19am how can you say that it is for kick back noise cancellation? Thanks, Rajasekhar. |
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