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Design >> RF Design >> Miltibit quantizer in SDM for a Fractional PLL
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Message started by boa on Jun 19^th, 2009, 4:41am

Title: Miltibit quantizer in SDM for a Fractional PLL
Post by boa on Jun 19^th, 2009, 4:41am

Hi all,

I have a question about the contribution of SDM to the output phase noise of a fractional-N PLL. In case we're using multi-bit quantizer in SDM loop (i.e. not only +1/-1, but more levels), does it give any advantage/disadvantage in terms of SDM's noise contribution?

In case of SDM ADC it is obvious, that the more number of bits we use, the smaller is the step between quantization levels, the smaller quantization error rms, i.e. delta^2/12 is. So increasing number of bits directly increases the resolution. However in a fractional PLL the division ratio step of prescaler is fixed to 1 (in case of N/N+1, let's not take fractional prescalers into consideration). So, according to my understanding, delta=1, no matter how much bits are there in quantizer.

I believe that multiple bits increase stability of the loop and make quantization noise closer to "white noise", that removing "idle tones" etc. But does it give any advantage in terms of noise contribution from SDM?

Title: Re: Miltibit quantizer in SDM for a Fractional PLL
Post by rf-design on Jul 11^th, 2009, 12:37am

Here

http://www.edaboard.com/viewtopic.php?t=147586&highlight=pll

is a more detailed discussion about multi-bit in frcational PLL. The zip contain also a comparison.