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Design Languages >> Verilog-AMS >> PFD verilog-A model question
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Message started by sch on Jun 23^rd, 2009, 2:10am

Title: PFD verilog-A model question
Post by sch on Jun 23^rd, 2009, 2:10am

Hi,ALL
I did not understand why the following verilog-A PFD of PLL can be described so simply.

integer state;
analog begin
@(cross(v(ref),+1,tttol) begin
if(state>-1) state=state-1;
end

@(cross(V(vco),+1,ttol) begin
if(state < 1) state=state+1;
end
I(out) <+ transition(Iout*state,0,tt)
end

Q 1 : what is the initial number of state?
Q2 : in ref ,why stste>-1 then stste=state-1
in vco ,why state<1 then state=state+1
sch

Title: Re: PFD verilog-A model question
Post by Geoffrey_Coram on Jun 24^th, 2009, 10:52am

A1. In Verilog-A, all variables start at 0.
A2. Then state=-1,0, or 1, and the current output is ±Iout or zero.