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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Phase Mrgin https://designers-guide.org/forum/YaBB.pl?num=1246096968 Message started by raja.cedt on Jun 27th, 2009, 3:02am |
Title: Phase Mrgin Post by raja.cedt on Jun 27th, 2009, 3:02am hi, can any body please tell me how to find degradation in PM because of delay in the loop? i saw in a pll thesis with td is the feedback delay wu is the unity gain loop bandwidth then phase margin degradation is 360*wc*td/2*pi..can any one please tell me why they are using wu..i thought its fref(input frequency) Thanks, Rajasekhar. |
Title: Re: Phase Mrgin Post by ywguo on Jul 1st, 2009, 10:07pm Rajasekhar, What we use is the offset frequency relative to the carrier frequency in small signal analysis for PLL. A constant delay in the loop means different phase delay for frequency ω1 and ω2. It has nothing to do with fref (input frequency). The phase margin degradation is caused by the additional delay at the unity gain frequency ωu. 360o*ωu*td/(2*pi). Yawei |
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