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Design Languages >> Verilog-AMS >> Testbench Verilog AMS
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Message started by brenox on Jun 27^th, 2009, 8:03am

Title: Testbench Verilog AMS
Post by brenox on Jun 27^th, 2009, 8:03am

Hi, my name is Breno and I am from Brazil, so I apologize about my English.
I am studying verilog AMS to implement an Analog to Digital Converter. My doubt is about how can I simulate an analog module? I tried to simulate some examples given in the page http://www.designers-guide.org/VerilogAMS/ but I only could simulate the examples with digital blocks running the script, because they come with the top module with the extension .vams and the testbench in .vams, or both in .v extension. But when I tried simulating an analog module, they come with the top module in .vams and the testbench in .scs extension. And the script is just “#!/bin/sh; spectre testbench.scs”. My question is:
- How can I simulate an analog module? Is it with the testbench in .scs?
- What is the script for doing the simulation? Is just the “spectre testbench.scs”? This command “spectre” is not recognize by the cadence simulator.
- Could you send me an example of an analog module with testbench, script and some prints of the waves resulted of the simulation?
- Can I make testbench in extension .vams for analog modules?
- Where can I find more about making verilog AMS testbenchs?

Since now, I appreciate. Thanks.

Breno

Title: Re: Testbench Verilog AMS
Post by Geoffrey_Coram on Jun 29^th, 2009, 11:55am

spectre should be in your linux/unix path, not a command known to the "cadence simulator" (what simulator is that, and how did you start it?).