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Design Languages >> Verilog-AMS >> What is the strict definition of a "compact model" ?
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Message started by engelbrl on Jun 30^th, 2009, 5:26pm

Title: What is the strict definition of a "compact model" ?
Post by engelbrl on Jun 30^th, 2009, 5:26pm

I need a true definition for a compact model. I have read a couple of papers by Geoffrey Coram, and it looks like a compact model must:

1) have electrical inputs and outputs,

2) use equations written to ensure only real, physical behavior (i.e. continuous derivitives), and

3) be relatively computationally efficient (compared to what..?)

So the above could probably describe "other" sorts of models - what transforms a Verilog-A/MS model into a "compact model" ??

This definition is needed for my Thesis presentation and I know I will be asked for a clear, defining difference between this term "compact model" and "other" behavioral models.... please help!

Thank you,
linda

Title: Re: What is the strict definition of a "compact model" ?
Post by Geoffrey_Coram on Jul 1^st, 2009, 11:32am

3) ... compared to TCAD simulation.

2) is, alas, only true for *good* compact models :)

I would say a compact model is a behavioral model intended as a lumped-element replacement for a single device in circuit simulation.

Title: Re: What is the strict definition of a "compact model" ?
Post by engelbrl on Jul 1^st, 2009, 2:44pm

Thanks Mr. Coram - I appreciate response AND the fast reply!

Linda