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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> clocked comparator design https://designers-guide.org/forum/YaBB.pl?num=1246619545 Message started by manodipan on Jul 3rd, 2009, 4:12am |
Title: clocked comparator design Post by manodipan on Jul 3rd, 2009, 4:12am Hi all, Actually i want some good references for clocked comparator design looking at speed,noise and offset of the comparator.The arhitecture used is clocked bottom transistor with NMOS input stages and regenerative load.I have designed using minimum transistor sizes and some offset compensation scheme will be used.But i have not found out any satisfying reference for designing this....thanks a lot. |
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