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Design >> Mixed-Signal Design >> digital component in CPPLL
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Message started by heaven_wb on Jul 6^th, 2009, 1:54pm

Title: digital component in CPPLL
Post by heaven_wb on Jul 6^th, 2009, 1:54pm

I am designing a integer N frequency synthesizer based on CPPLL. I am confused how to design digital component. For example, PFD actually consists of D-FF and some gates. Shall I design it by verilog then synthesize it or design it in transistor level as usual? In addition, for divider, there is the same problem. The value of divider is about 2400. Is Verilog-A useful for this situation? Thank you very much.

Title: Re: digital component in CPPLL
Post by raja.cedt on Jul 6^th, 2009, 9:24pm

hi,
it depends on your operating frequency, generally synthesized block wont work at high frequency..may be PFD will work because it is working at reference frequency, but divider has to work at high frequency

Thanks,
Rajasekhar.

Title: Re: digital component in CPPLL
Post by heaven_wb on Jul 7^th, 2009, 12:57pm

Thank you very much. The reference frequency is 1 MHz, the output frequency is 2.4GHz. another problem: can I design divider by Verilog-A? The simulator is cadence spectre. the simulation with Verilog-A seems to run, but I don't know how to deal with the information about circuit speed. verilog-A is just for simulation in mixed-signal design or can be used be synthesized into circuit? Thank you very much.

Title: Re: digital component in CPPLL
Post by raja.cedt on Jul 7^th, 2009, 10:26pm

it is always better not to use synthesized ckts in plls..if you want you can try for PFD..but not for divider.

Thanks,
Rajasekhar.

Title: Re: digital component in CPPLL
Post by heaven_wb on Jul 8^th, 2009, 12:04pm

OK, Thank you very much. I will follow your idea.

Title: Re: digital component in CPPLL
Post by raja.cedt on Jul 8^th, 2009, 9:44pm

And one more thing why you are using 2400 divider (its too big), don't you have high reference frequency...because aftre your you may see very bad noise performance from PLL.

thanks,
Rajasekhar.

Title: Re: digital component in CPPLL
Post by heaven_wb on Jul 9^th, 2009, 5:58am

Thank you very much. We will pay attention to it. Because our architecture is interger N not franctional, but we need 1-MHz spacing frequency and 2.4GHz output frequency. So the reference frequency could be only 1MHz, and divider is 2400.

Title: Re: digital component in CPPLL
Post by raja.cedt on Jul 9^th, 2009, 9:26am

k that's fine for what application this pll..and you could have use Fractional

Thanks,
Rajasekhar.

Title: Re: digital component in CPPLL
Post by wave on Jul 9^th, 2009, 10:03am

heaven_wb wrote on Jul 6^th, 2009, 1:54pm:

From the question, I'd suggest you find a mentor who has gone thru this before.
The PFD should be custom not synthesized with standard cells. For jitter and lock, you have dead zones and rise/fall symmetry to worry about.
Depending on process, you'll probably need custom dividers for the first few stages (ie, CML), until standard logic is fast enough. Probably best to use custom cells there too.

I agree you'll want a higher Refclk frequency. Maybe 100MHz.
I haven't worked with Frac-N much, but sounds like a way to go.

Certainly you can and should do higher level modeling of all and parts of the loop --- matlab, verilog/verilogA, etc.

Good luck.
Wave
:)

Title: Re: digital component in CPPLL
Post by oermens on Jul 9^th, 2009, 3:05pm

wave wrote on Jul 9^th, 2009, 10:03am:

Depending on process, you'll probably need custom dividers for the first few stages (ie, CML), until standard logic is fast enough.

How do we determine this? Hypothetical situation: Lets say I need to divide by 128 and my frequency is 3200MHz, do i start with all std logic and if the first stage does not operate fast enough, replace it with high speed logic and so on until the std logic is sufficient? Is there some empirical result we can use?

Title: Re: digital component in CPPLL
Post by wave on Jul 9^th, 2009, 4:02pm

oermens wrote on Jul 9^th, 2009, 3:05pm:

wave wrote on Jul 9^th, 2009, 10:03am:

Depending on process, you'll probably need custom dividers for the first few stages (ie, CML), until standard logic is fast enough.

Basically yes.
Consider your f_T and Gm of your PMOS device. If it's fast enough, you can use standard CMOS gates. If not, you'll have to go to an NMOS signal path (CML).
"enough" is qualified by slew rate, with picks up noise(s) during a logic transition and creates jitter.
PLL jitter should not be dominated by a divider.

Wave
;D