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Modeling >> Behavioral Models >> VCDL Verilog-A/AMS Model
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Message started by Ahmed Nassar on Jul 11^th, 2009, 11:36am

Title: VCDL Verilog-A/AMS Model
Post by Ahmed Nassar on Jul 11^th, 2009, 11:36am

Hi all,

Can anyone kindly provide me with a Verilog-A/AMS model of a voltage-controlled delay line?
I know this is a DISTRIBUTED component, but there might be a good lumped-model approximation for it.

Thanks,
Ahmed

Title: Re: VCDL Verilog-A/AMS Model
Post by Ahmed Nassar on Jul 19^th, 2009, 6:07am

I found the solution:

One can use the Verilog-A "delay()" function or the Verilog-AMS "absdelay()" function with the maxdelay parameter passed properly and letting the delay value be varying.

The maxdelay parameter is the key to let the delay value passed to this function be varying. If this parameter is not specified, the delay introduced by either of those functions is not allowed to vary. It seems that maxdelay is used to allocate a fixed amount of buffer space in memory to store all signal values in the delay interval.