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Design Languages >> Verilog-AMS >> setup-time measurement
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Message started by idriss on Jul 13^th, 2009, 6:33am

Title: setup-time measurement
Post by idriss on Jul 13^th, 2009, 6:33am

hello everybody,

I saw that we could check the setup and hold time with verilogams by using the task function $setup within a specify blockand if there is a violation during the simulation it will pop up a warning violation message like this one :

Warning! Timing violation
$setup( d0:67617224878 FS, posedge cn:67617405534 FS, 200 : 200 PS );
File: ./ihnl/wpan_cln45_dpll_lib/wpan_cln45_dpll_dds_mux2/verilogams/verilog.vams, line = 53
Scope: wpan_cln45_polar_ams_tb.DPLL_0.div2p5_dds.mux2_2
Time: 67617405534 FS

what I would like to know if it's possible in a model code to measure the setup time and check whether there's a violation to the setup time and if yes assign a X to the outputlike, see the model below and the comments .

reg violation

specify // here to check if the setup time is ok
$setup(d0, posedge cn,200);
endspecify

**how to get a value to violation**???? in order to use it in the following always block,how to extract infos from this specify block??

always @( cn or cp or d0p or d1p)

begin

op = #tdelay (!violation) ? ((cn && d1p) || (cp && d0p)):1'bx;
on = ~op;

end

Thank you very much in advance
Idris

Title: Re: setup-time measurement
Post by jbdavid on Jul 14^th, 2009, 10:12pm

I think if that would have been valuable, it would be in the language already. $setup was the way timing violations were flagged before STA came into vogue.. its really pretty old, as verilog goes.. it was probably in Verilog-1995 even before Verilog-A was first ratified..

making the output x would NOT be a good idea.. since it should (these days where LOW POWER is the design driver) only go to X when really UNK or the gate is not powered (or VDD is too low for the gate to work properly)

and $setup is NOT setup to give you ACCESS to a setup time measurement, just to FLAG it if the setup time is violated.
good luck
jbd

Title: Re: setup-time measurement
Post by idriss on Jul 15^th, 2009, 2:25am

Hi JbDavid

Thank yo for your reply,
actually what I need is a flag to warn me whether I violated the setup time and I think $setup is doing that,I found out that you could add a notifier in order to get a reg signal ,the only stupid thing about that,it toggles each time there is a violation, it means if before the violation the notifier is level 1 after the violation it will become 0 and vice versa ad when there is no violation the value of the notifier doesn't change.
The issue is how to use it within my code
because I need to say each time there is a violation put the output op to X ,do you have an idea,I checked for vhdl they have this function called d'stable and it's much more easier they don't toggle anything like within verilog.
Maybe there is an other way to check whether I have the correct setup time in verilog,do you have an idea ?
Thank you very much

reg notifier

specify // here to check if the setup time is ok
$setup(d0, posedge cn,200,notfier);
endspecify

always @( cn or cp or d0p or d1p)

begin

op = #tdelay (!violation) ? ((cn && d1p) || (cp && d0p)):1'bx; // if there is a violation of the setup time between cn and d0 put op to x
on = ~op;

end