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Modeling >> Behavioral Models >> Frequency Resolution of a PLL is bound by timescale of VerilogAMS - advice?
https://designers-guide.org/forum/YaBB.pl?num=1247658179

Message started by Alexander Eßwein on Jul 15^th, 2009, 4:42am

Title: Frequency Resolution of a PLL is bound by timescale of VerilogAMS - advice?
Post by Alexander Eßwein on Jul 15^th, 2009, 4:42am

Hello,

I'm working on a PLL design with behavioral models in VerilogAMS. I encountered a problem where it seems that the minimum timescale of 1 fs is not accurate enough to generate the exact desired frequency of my VCO.

The tuning voltage of my VCO does not get integrated to the precise value I need - namely 0V for a frequency of exactly 5.8 GHz (25MHz Fref, N = 232).

Is there any way to improve the frequency resolution by maybe circumventing the minimum timescale?

Thanks in advance,
Alexander Eßwein

Code:

`timescale 1ps / 100 fs
`include "disciplines.vams"

module vco_1 (out_rf, out_div, ps, ns);
parameter real f0 = 5.8G from (0:inf); // center frequency (Hz)
// parameter real fmax = 6.3G from (0:inf);
// parameter real fmin = 5.3G from (0:inf);
parameter real kvco = 25M; // gain (Hz/V)
parameter real maxcount = 232;
input ps, ns;
//input DCO_CONTROL_S;
output out_rf, out_div;
electrical ps, ns;
//logic [7:0] DCO_CONTROL;
// logic DCO_CONTROL;
//logic DCO_CONTROL_S;
reg out_rf;
logic out_rf;
reg out_div;
logic out_div;
real vin;
// real din;
integer count;
real freq;

initial begin
out_rf = 0;
out_div = 0;
count = 0;
end //initial

always begin
vin = V(ps, ns);
#((0.5e12 / (f0 + kvco * vin))) begin
out_rf = ~out_rf;
end //delay
end

// DIV frequency generation by means of a counter
always @(posedge out_rf or negedge out_rf) begin
freq = f0 + (kvco * vin);
count = count + 1;
if (count == maxcount) begin
out_div = ~out_div;
count = 0;
end //if
end //posedge OUT_RF

endmodule

Title: Re: Frequency Resolution of a PLL is bound by timescale of VerilogAMS - advice?
Post by jbdavid on Jul 16^th, 2009, 5:58pm

you'll either have to work with Analog side signals, or
delve into the source code for the simulation and add the "as" timescale resolution I first requested from cadence years ago..
not using a simulator with available source code?
File another bug report with the Cad guys.. they'll try to complain that "as" timescales are not in the Language spec. and it'll take years to get a change to the language spec..

there is one other way to do it..
the math to calculate the desired period doesn't drop digits..
you can track the error in the period, and, when it accumulates to at least the minimum timescale, add it back in..
as long as stays under your jitter sensitivity you should be ok..

you'll get the right Average frequency .. by dithering the (quantized) instantaneous frequency around the desired value with the right duty cycle.

good luck!
"burned already"
jbd