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Design Languages >> Verilog-AMS >> segmentation fault when I simulate a verlioga opamp model
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Message started by hhd1983 on Jul 28^th, 2009, 8:50pm

Title: segmentation fault when I simulate a verlioga opamp model
Post by hhd1983 on Jul 28^th, 2009, 8:50pm

Hi, I wrote a simple opamp model with veriloga,

module test(in, ip,out);
input in,ip;
output out;
electrical in, ip, out;
parameter gain = 10000;
parameter bw = 100;
analog begin
V(out) <+ laplace_nd(V(ip,in),{1},{1,1/(2*3.14*bw)});
end
endmodule

But the simulator tell me a segmentation fault when I simulated it with spectre.
Can somebody help me? thanks.

Title: Re: segmentation fault when I simulate a verlioga opamp model
Post by Andrew Beckett on Jul 30^th, 2009, 5:25am

You'll need to give more than that. I just threw together a simple testbench, and it simulated OK in MMSIM71.

So, you'll need to give the spectre netlist you're using, and ideally the subversion of spectre you're using (type "spectre -W").

Regards,

andrew.

Title: Re: segmentation fault when I simulate a verlioga opamp model
Post by hhd1983 on Jul 30^th, 2009, 7:21pm

Thanks for the reply.

The subversion of spectre is 5.10.41_USR3.102405, and the netlist is:

Quote:

I7(in ip net15) test gain=10000 bandwith=5M
C0(net15 0) capacitor c=1p
E1(ip 0 net3 0) vcvs gain=0.5
E0(in 0 net3 0) vcvs gain=-0.5
V0(net3 0) vsource mag=1 type=sine ampl=10m freq=5M

ahdl_include "/home/xxx/xxx/test/veriloga/veriloga.va"

analysis type "tran" "dc" "ac"

The file veriloga.va is:

Quote:

module test(in, ip,out);
input in,ip;
output out;
electrical in, ip, out;
parameter gain = 10000;
parameter bw = 100;
analog begin
V(out) <+ laplace_nd(V(ip,in),{1},{1,1/(2*3.14*bw)});
end
endmodule

That's all.
Regards.

Title: Re: segmentation fault when I simulate a verlioga opamp model
Post by hhd1983 on Jul 30^th, 2009, 7:25pm

I find that it's no fault when I simulate it in Cadence 5.0.33. Is it a tool version problem?

Title: Re: segmentation fault when I simulate a verlioga opamp model
Post by Andrew Beckett on Aug 12^th, 2009, 2:25pm

Both the IC5141 version and 5.0.33 are old (really unsupported) versions of spectre.

That said, I don't see the problem in the latest IC5141 version of spectre, nor with a more recent version (e.g. MMSIM71).

That said, you didn't include the complete netlist including analysis statements, so it's hard to be sure. I just used a somewhat arbitrary transient analysis, but I don't know what you were doing.

Also, your instance line for I7 uses a parameter "bandwith" (spelt wrong), whereas the veriloga has "bw". Not sure if that's relevant...

I tried it both as "bandwith" and "bw" and it worked in both cases for me.

So probably best just to try a more recent spectre version.

Regards,

Andrew.