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Measurements >> Phase Noise and Jitter Measurements >> how to simulate the Digital Delay Lock Loop's jitter or phase noise
https://designers-guide.org/forum/YaBB.pl?num=1248855694

Message started by fmcarol on Jul 29^th, 2009, 1:21am

Title: how to simulate the Digital Delay Lock Loop's jitter or phase noise
Post by fmcarol on Jul 29^th, 2009, 1:21am

Hi All，

I want to simulate the "Output Jitter", is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.

I use "PSS+Pnoise" simulate the circuit, but I confuse with some choices in Pnoise window.

1.Output Frequency Sweep Range(Hz)
star ??Hz stop ??Hz

What shoule I fill?

2.Input Source:Voltage, Current, Port, None.
Which shoule I select?

Thanks,
carol