The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> failing to declare pins as global signals
https://designers-guide.org/forum/YaBB.pl?num=1248994742

Message started by Dipankar on Jul 30^th, 2009, 3:59pm

Title: failing to declare pins as global signals
Post by Dipankar on Jul 30^th, 2009, 3:59pm

Dear Sirs,

I am using a CDK whose cells have schematic, symbol, layout and functional (verilog) views. Now for all the cells sch view has VSS and VDD inout pins (not globals) but the symbol views don't have them. My problem is I am failing to declare VDD and VSS as global from ADE. When I use functional view of those cells, simulation(AMS) goes smoothly, but when I use schematic view of those cells simulation fails just because the cells' power grnd pins are not getting the desired voltage supposed to get passed to them from TOP testbench. Please advise.

Title: Re: failing to declare pins as global signals
Post by Andrew Beckett on Aug 15^th, 2009, 1:19am

So do the pins on the schematic have inherited connections? If they're not global signals, and they're not inherited connections (i.e. have net expressions on them) it's rather hard to see how you'd connect to them.

The AMS netlister should handle inherited connections OK.

I think you'll need to give some more details - perhaps some pictures - for us to be able to help. At least to avoid me having to anticipate every possible scenario you might have...

Best Regards,

Andrew.