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Design Languages >> Verilog-AMS >> Convergence Problem
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Message started by Deb on Aug 3^rd, 2009, 12:46pm

Title: Convergence Problem
Post by Deb on Aug 3^rd, 2009, 12:46pm

Hi All,

I am having the following peculiar problem while using the Verilog-A model. I have a schematic which contains two buck circuits. Currenly I have modeled the BUck in the mode based modeling method rather than component based modeling. That is I have modeled the Buck using the different mode thorugh which it passes like Shutdown, Startup, PWM, PFM etc. Whenever I simulate the schematic in spectre, spectre does not complain about any convergence problem. But as soon as I replace the schematic by verilog A model using Hoerarchy editor in Cadence, spectreVerilog complains about the convergence...Actually my aim is to verify top level connection...Is it a modeling problem? Can any one suggest a suitable solution for this?

Title: Re: Convergence Problem
Post by Peruzzi on Aug 5^th, 2009, 10:54am

Deb,

If all you really want to do is verify connectivity you can vastly simplify and speed up the model by eliminating all functionality, and simply use assertions to monitor and report changes to inputs. Then drive outputs in conjunction with downstream models monitoring their own input connectivity.

However, sometimes they don't really mean it when some folks say they only want to verify connectivity.

You may contact me directly if you'd like further information.

Cheers,

Bob P.
www.RPeruzzi.com

Title: Re: Convergence Problem
Post by Deb on Aug 5^th, 2009, 11:15am

Hi,

How can I contact u directly? Can you please provide me your direct email ID? I really want top level verification of the integrated circuit.

Cheers
Debjit....

Title: Re: Convergence Problem
Post by rajdeep on Aug 21^st, 2009, 3:45am

Hi Debjit,

It heavily depends on the size and mostly on the environment in which your model is being used. A buck model that works in a particular environment might have convergence problem when you put it in an integrated circuit. For top level integrated circuit such as a PMU (?) it is better to have very simple models, as suggested already. You may require to have models of different complexity for different situations. For top level connectivity verification I think one should have very simple models. May be omit stuff like PFM. Just flag a message that the block enters PFM, thats it!!!
This can speed up the whole simulation vastly, and also will have less trouble for the simulators to converge!

Finally, the simulator is also responsible for causing these convergence issues. It may not be entirely that the models are wrong. But then one of the biggest challanges is to develop a model that works in the given simulator. I assume you are using spectreVerilog (not only spectre) for top level sims. spectreVerilog is even more notorious when it comes to convergence!

Having said all these, it is undoubtedly good to have Verilog-A models that models many behaviors and yet helps quick simulation at chip level!!! But then time flies... :-X

hope that helps..
cheers!
Rajdeep