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Design >> Analog Design >> what induce doublets in gain boosting technique in deed?
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Message started by xwj623 on Aug 5^th, 2009, 7:34pm

Title: what induce doublets in gain boosting technique in deed?
Post by xwj623 on Aug 5^th, 2009, 7:34pm

i can't quite understand why gain boosting present doublets,
and what induce it in deed.
Though i have read the "A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain" , i can't understand the FIG 4.
Are there anyone who explain this to me.
thank you.

Title: Re: what induce doublets in gain boosting technique in deed?
Post by raja.cedt on Aug 5^th, 2009, 9:21pm

hi,
have you understand these impedance plots intuitively? i mean how gain boosting impedance curve looks like....if so impedance plot has a zero at the boosted amplifier ugb , and output cap impedance decrease with 20db/dec........Net output impedance is th e parallel combination of both..so finally impedance has to follow cap impedance .that means you there is no pole and zero..but already there is a zero, so as to compensate that there should be a pole.
Hope it helps ..if you have any doubts let me

Thanks,
rajasekhar.

Title: Re: what induce doublets in gain boosting technique in deed?
Post by vivkr on Aug 6^th, 2009, 12:15am

xwj623 wrote on Aug 5^th, 2009, 7:34pm:

Hi there,

The net output resistance (note that I stress on the word resistance) of a gain-boosted cascode is approximately

(1+Gboost)*Rout,cascode

At DC, Gboost is very high and it starts to roll-off as the frequency increases and you approach the unity-gain point of the boosting amplifier. Beyond that point, the net resistance flattens to Rout,cascode.

In other words, the impedance is first flat at a high level at very low frequencies, starts to roll off (a pole) and then flattens out again (a zero). This is all the auxiliary loop. In the main amplifier, you have a pole due to the gm of your opamp and the output load cap. So you have a pole-zero doublet.

Note however that the presence of the zero is the more critical part for settling since closed-loop poles are always attracted to open-loop zeros. So as long as you have open-loop zeros at a frequency lower than the closed-loop bandwidth, you will experience settling problems due to these.

By the way, the paper by Bult and Geelen explains the whole thing quite well. Go through it again, and also try Tom Lee's book on RFIC design. He covers this part there as well although not in the context of gain boosting.

Regards,

Vivek

Title: Re: what induce doublets in gain boosting technique in deed?
Post by raja.cedt on Aug 6^th, 2009, 1:33am

hi vivkr,
in which contest THLEE has given..i want see it

Thanks,
Rajasekhar.

Title: Re: what induce doublets in gain boosting technique in deed?
Post by vivkr on Aug 7^th, 2009, 12:53am

raja.cedt wrote on Aug 6^th, 2009, 1:33am:

hi vivkr,
in which contest THLEE has given..i want see it

Thanks,
Rajasekhar.

Hi Rajasekha,

I don't remember exactly but look in the sections dealing with lead/lag compensation. That should be in the chapter dealing with stability and compensation. But you don't need to see the book for that. Just think of a root locus. Here, the closed loop poles start where the open-loop poles were and end where the open-loop zeros were. By the way, this side discussion is now deviating from the original doublet discussion.

Regards,

Vivek

Title: Re: what induce doublets in gain boosting technique in deed?
Post by raja.cedt on Aug 7^th, 2009, 2:21am

hi xwj623,
i think this explanation will help you better, from the fig you see net impedance is the parallel combination of both, so net impedance has to follow minimum of the both...that means you will get a pole at p and from there it has to follow cap impedance so there must no pole and zero furthermore .But in the amplifier Zout we have a pole...that some zero has to be there in the system exactly at the pole of the amp such that it cancels the pole.

Hope this helps

Thanks,
Rajasekhar.

Title: Re: what induce doublets in gain boosting technique in deed?
Post by vivkr on Aug 7^th, 2009, 6:49am

raja.cedt wrote on Aug 7^th, 2009, 2:21am:

Hi Rajashekhar,

Unfortunately, your figure is not quite complete and in any case, there is quite a good figure showing how the output impedance varies with frequency in the very first post of this thread, although the doublet itself is not visible from either as I have already mentioned in my first reply.

Regards,

Vivek

Title: Re: what induce doublets in gain boosting technique in deed?
Post by xwj623 on Aug 8^th, 2009, 6:56am

thanks raja. your figure explain the output impedance very clearly.
i have understand it. :)

raja.cedt wrote on Aug 7^th, 2009, 2:21am:

Title: Re: what induce doublets in gain boosting technique in deed?
Post by xwj623 on Aug 8^th, 2009, 6:57am

yes,vivkr.
i agree with you.

vivkr wrote on Aug 7^th, 2009, 6:49am:

raja.cedt wrote on Aug 7^th, 2009, 2:21am:

Title: Re: what induce doublets in gain boosting technique in deed?
Post by nobody on Aug 9^th, 2009, 7:38pm

I am with Vivek. The figure provided by xwj623 is from Bult, I believe.

Title: Re: what induce doublets in gain boosting technique in deed?
Post by raja.cedt on Aug 9^th, 2009, 8:17pm

hi vivkr and nobady,
i agree with you..i just want to give a trail with some kind of wage explanation with out going into much circuit details..., in fig i forgot to add doublet at Z.

Thanks,
Rajasekhar.