The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> help me to evaluate my simulation result
https://designers-guide.org/forum/YaBB.pl?num=1249901093

Message started by icekalt on Aug 10^th, 2009, 3:44am

Title: help me to evaluate my simulation result
Post by icekalt on Aug 10^th, 2009, 3:44am

Hello everyone,

Please see my output waveform of my comparator in attachment. The comparator should make decision when the clock (Vclk) is low. Vp and Vn are the input of my comparator.Vout- is the output of my comparator. If you see the waveform, the output will be 3.3 although Vn is greater than Vp at certain time. For example, at 224.959ns, Vp is greater than Vn, but the comparator is in reset(no decison) in this time and the Vout- is appr. 1.7 V and it is fine. But when the clock is low, instead of comparing the present value of Vn and Vp, it compares the previous value of Vn and Vp that is at 224.959ns. Is this result ok or no? Is this what we called latency problem?

Thx in advanced

Title: Re: help me to evaluate my simulation result
Post by mikro on Aug 18^th, 2009, 6:50am

if i were u, i will recheck the logic vs schematic .

if u wanna compare the inputs, which were present shortly before low-active, it is fine.

if u wanna compare the inputs, which are present during low-active, it is not fine.

Title: Re: help me to evaluate my simulation result
Post by Berti on Aug 18^th, 2009, 10:42pm

Latency problem? Never heard!

To me it looks more like that your comparator has a large hysteresis. Reasons might be incomplete reset or bad settling of reference voltages.

Cheers