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Simulators >> Circuit Simulators >> set logic to 0V at simulation start
https://designers-guide.org/forum/YaBB.pl?num=1249919089

Message started by tempora123 on Aug 10^th, 2009, 8:44am

Title: set logic to 0V at simulation start
Post by tempora123 on Aug 10^th, 2009, 8:44am

hello,

I would like to run top level mixed signal (spectreVerilog) simulation where the power supply is ramped up from 0 to vdd. I need to reset all nodes inside the circuit to a known state because now I get unknown states for some internal nodes and spectre doesnt converge. Is there any switch (+sdf... or other way) I could use in the Simulation -> Options -> Digital tab to reset all nodes to 0V?

Thanks for your help.