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Message started by ycm on Aug 12^th, 2009, 4:41pm

Title: high oversampling ratio
Post by ycm on Aug 12^th, 2009, 4:41pm

for designing a high resolution delta sigma ADC, if the input to ADC is low frequency signal say 1kHz, if I use first order single bit with very high sampling frequency say 100MHz (OSR=50000), I can achieve a SNR over 140dB. I can also using higher order modulator to achieve the similar SNR. what is the disadvantage by using first order modulator here?

BTW: How do you get the conversion time for one sample in delta sigma ADC?

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 2:06am

Your Sampling Speed is too high.
Following are the problems you will face.
1.The biggest problem is the noise transfer function. The quantizer white noise will be quite high at the output. For first order SDM cutoff at your corner frequency for the NTF will be quite high. To lower this you ned very high gain OPAMP.

2.Second problem is you need an OPAMP with very high bandwidth(because your sampling rate is too high), which will be difficult to achieve.

3. Most probably you will be using a single bit quantizer, this will reflect the jitter noise.

4. the KT/C noises of your switch.

5. The buffer SNR Bottleneck

6. OPAMP noise.

7. Your OPAMP slew rate requirement would be very high.

8. Your hysteresis errors at the quantizer output.

9. DAC error.

10. Bandgap error

11. Most Importantly your Bandgap noise.

I would like to suggest you a feasibility study using systemc-ams and systemc.

Please let me know if you need further help.

Keep posting,
Regards,
Sumit

Title: Re: high oversampling ratio
Post by Berti on Aug 13^th, 2009, 6:08am

Hi Sumit, I have problems understanding many of your comments.

It is not impossible to design a DS modulator with a sampling frequency of 100MHz. I have designed modulators with fs>200MHz. But probably it is not the most power efficient solution. Furthermore, 1st order modulators are famous for artifact like idle tones.

Quote:

1.The biggest problem is the noise transfer function. The quantizer white noise will be quite high at the output. For first order SDM cutoff at your corner frequency for the NTF will be quite high. To lower this you ned very high gain OPAMP.

Sumit, can you please elaborate on that?!

Quote:

3. Most probably you will be using a single bit quantizer, this will reflect the jitter noise.

That depends whether it is a continuous-time or a discrete-time implementation.

Regards

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 6:14am

thanks for your inputs, Sumit,

Do you know how to find the conversion time for a delta sigma converts?
for example, given a input Vin, how fast we can get the output for a 16bit delta sigma ADC if OSR and bandwidth of Vin(Fin) are known?

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 6:19am

[quote author=Berti link=1250120511/0#2 date=1250168890]Hi Sumit, I have problems understanding many of your comments.

It is not impossible to design a DS modulator with a sampling frequency of 100MHz. I have designed modulators with fs>200MHz. But probably it is not the most power efficient solution. Furthermore, 1st order modulators are famous for artifact like idle tones.

Yes, idle tones can degrade the performance of the converts, but how bad can that go? say if the ideal snr is 140dB, from your experience, the final circuit will give out a snr around what value? 100dB? thanks.

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 7:00am

Hello Berti,
Thanks for sharing your experience. My question is that did you
design first order sigma delta modulator meeting SNR > 140 dB ?
It would be amazing to see the topology. Can you please share ?
I am eager to see the Monte Carlo results also. I never said that
it is impossible. But I never designed first order SDM system.
Well my experience is quite limited and I have only worked on it for
last seven years in which I only addressed second order or higher.
It was my mistake that I considered it as a discrete time modulator.

Hello YCM,
Calculating conversion time is absolutely possible. My question is
do you want t for the modulator only or for entire ADC ?
Your transfer functions of various stages gives you estimate of
of total delay and conversion time. Let me know how can I help
you. It would be a pleasure of mine to assist you.

For your Idle tone problem you may use dithering. Followings are the
types which might interest you :
1. Noise-Shaped Dithering
2. Subtractive Dithering
3. Dynamic Noise-Shaped Dithering
4. Adaptive Bit Flipping Dithering

Best Regards,
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 8:39am

Thanks Sumit, you long time experience will definitely help. Can you educate me for the following questions?

1. It is practical to use first order single bit delta sigma delta sigma ADC with 16 bit resolution, given low input signal bandwidth say 1kHz? what kind of OSR (margin) is going to be needed to achieve the target SNR in real circuits?

2. if it is practical to design above ADC, to achieve 16 bit resolution, given input signal bandwidth 1kHz, sampling frequence is OSR*2fin, say 1MHz. Can we get conversion time for the whole ADC based on these information? if we can not, what extra conditions do we need and then how to get the whole conversion time?

3. if it is not practical to design above ADC, for second order single bit delta sigma ADC given the same conditions in question 2, how to get the conversion time of the whole ADC?

Thanks.

Ycm

Ycm

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 9:16am

Hello YCM,
Thanks for the interest. Well I am a system designer. I look into things
more theoretically. We should account for each delays and calculate
things exactly.
Firstly we need to know where is the delay (clocked
delay) in your SDM ? . Mean are you using the delay in integrator
or dac or in quantizer or in all. If you have delay in integrator
( H(z) = 1/z-1) then the total delay in SDM signal path is one. If it is
both in Integ and quant then the delay is 2. If your
Integ H(z) = z/z-1 and quant is clocked then total delay due to
SDM is one. Clocked DAC does not contribute to the signal path
delay of SDM, it only affects STF,NTF and Stability of system.

2. Second point is CIC (considering you will be using a CIC to
gain some number of bits). Look at this well. For a SDM of Order
K the order of CIC required is L = K + 1
For first Order K = 1 and L = 2.
For Second Order K = 2 and L = 3 .
This means the CIC will have L number of integrators and L number
of differentiators. Now look at differentiators carefully. Each
differentiator is a symmetric FIR filter. For a symmetric FIR filter of
N coefficients the group delay is N/2. For a differentiator it will
be 1/2. Half delay!!!!! and you will have to compensate that. In your
case you have 2 differentiator stages, which will produce
1/2 + 1/2 = 1 delay (in decimated data rate). But you have a
previous delay of one (probably) from SDM, two more delays
( probably) from two integrators and 1 delay at the down sampler
(probably), all in SDM sampling rate. So altogether 1 + 2 + 1 = 4
delays and you will have to match that. You will have to match
these delays to get 1 (for differentiator) + 1 (for this calc).
The way you can do this is, say you down sample in first CIC
stage by a rate N. Then to accomodate these 4 delays into CIC is
put a delay stage of N-4 beore CIC(at SDM clock rate) to get 2
clock cycle at the output of CIC(with downsampled rate). So you
got rid of fractional delays and got integral delay at CIC output.

3. Continue this for next CIC stages.

4. Try to fit a Symmetric FIR(If you are interested in it at all) so that
the group delay would N/2. And you know if you have a FIR, that
poses the conversion delay bottle neck. Add all the delays (for
each block) and you get the conversion cycle :)

What are the next stages. How you are planning them.
Please let me know how is your downsampling and filtering scheme

Best Regards,
Sumit

P.S. : Just Checked your second order SDADC part. Well in most of the cases it would be the FIR(If you have at all) group delay.
It is absolutely possible to gain 16 bit resolution with your spec.
If I understand this spec is for some low frequency sensor application.
If it is true then you will have something called chopping (which will be
more crucial that other things). Chopping imposes some limitations
on DSP of ADC.
Well for this spec OSR of 1024 is sufficient. in safer side 2*1024
would be more interesting. In that case I would suggest a SDM
clock of 2MHz if possible.

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 9:52am

Many thanks,

Yes, for input signal bandwidth 1kHz, I can even use a sampling frequency 1MHz (OSR=500) to achieve 16 bit resolution for a second order single bit modulator. If I use a counter as a decimation filter to count 2^16 clocks to get a 16 bit output, here, do I need follow the rule OSR=2^16 ? given Toversampleclk=1us, what will be the total conversion time for the whole ADC?

BTW why OSR for most cases, people use 64, 128, ... why not 10, 100 something like that?

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 10:02am

I would like to give answer of last question first.

The decimation is in digital domain and downsampling by power of two is more easy. Thats why OSR is given as power of two. It is also possible to
downsample by any ratio, but it complicates the decimation circuit by
introducing interpolators in them.

For first question. I must confess that I did not understand your question well. If you want to down sample by using a counter only then you have some other problem/ If i understand it well then you will accumulate (integrate) inputs for N number of samples and then
give out one sample. But integrator alone has some problem. It has a pole at z = 1. It means the circuit will be unstable at dc. To use this efficiently you need to compensate this pole. Thats why using a differentiator(which introduces a zero at dc and compensates the pole).
If your output sampling rate is 1kHz and SDM sampling clock is 1MHz any way
you will have to downsample by 1024, then why not using the advantage. Note you will have to select a SDM clock which after
dividing by 1024 produces 1 kHz outpu sampling rate, which is not accurately 1MHz :)

For your conversion delay question, it is very important to know
your decimation scheme to answer this question

Regards,
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 10:20am

got you.

for the first question, I see some block diagram(see attached picture) for the first order single bit application. for this diagram, what is the conversion time for the ADC if we ignore the delay in the modulator. then the conversion time for a 16 bit will be 2^16*Tclk. but, do we need to follows N=OSR here? if that is the case OSR will be very high for the system.

Please let me know what do you think. thanks.

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 10:39am

This diagram is not detailed and very much symbolic. simply lesser
sampling rate registered output wont give you any meaningful output.

Let us consider that "register" block as CIC. Then if you dont even have
delay compensation for integrators of cic then you have approximately(this term is very important) 1 delay of CKN cycle.

by the way you need to enter detailed study analysis and you are
at a very initial stage :). Everybody needs to start from somewhere.
It is very good that you want to clear your concept about everything.
I liked this :)

Regards,
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 11:00am

Thanks Sumit

the output of the ADC is the bitstream. if input to the ADC is 3/4 of the full range, its output will be '1011', its DC average is 3/4 which is corresponding to the input signal to the ADC. The counter counts 4(2^2) clocks and the output of the counter is 2-bit binary format '11' which can be considered as the binary fraction between 0 and 1. This binary output '11' is stored in the register as the ADC output ('11' means 3/4 =1/2+1/4).

In this example, what do you think for my original questions about conversation time? Thanks

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 11:05am

One cycle of CKN will be your delay

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 11:42am

Thanks for your reply. some of the concept are clear now to me. Let me ask one more thing:

design requirements: resolution; 16-bit; input signal bandwidth 1kHz; conversion time: 1ms;

I want to use first order single bit ADC with the decimation filter I mentioned above. Is it practical to achieve such as requirements with relative low OSR say 1024*2kHz sampling frequency as you mentioned? if not, how about second order single bit?

Appreciate your help
Ycm

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 11:58am

For second order single bit it is absolutely possible.
For first order you need to do a feasibility study. There are few things
you need to keep in mind, some basic thumbrules.

SNR > 70 dB : Consider First Order Non Idealities.
SNR > 100 dB : Consider Upto Second Order nonlities
SNR < 140 dB : Consider all kind of non idealities.

Therefore I would suggest you to do a feasibility study over First Order Sigma Delta Modulator. This can be done using a model and introducing non-idealities.

Matlab/Simulink could be one such tool. But the controllability while using macros will be bad. Speed is also not good. You may please considering modeling in systemc-ams. You will get an estimate of how much SNR is posible.
If not satisfied with systemc-ams + systemc model result or still the result lies in boundary, further detailed modeling in verilog-ams can
be done. This is how you should proceed. Entering circuit designing stage will be far later. You should spend more time in modeling and
analyzing model results. Rigorous study on models with high reliability
can be done with ease while rigorous study on circuits is impossible.
If you end up with modeling in verilog-ams you will be having a reference design for each block which can be verified against each designed blocks in circuit level. This will also reduce your number of re-spins.
Let me know if I am missing something.
Regards,
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 13^th, 2009, 3:17pm

Thanks, this is really helpful.

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 13^th, 2009, 11:34pm

Please let me know if you need help in system designing/modeling/simulation and also regarding documents.
Happy to help,
Sumit

Title: Re: high oversampling ratio
Post by Berti on Aug 14^th, 2009, 3:30am

Sumit, 7 years experience is a lot!
The fs>200MHz delta-sigma modulator I designed was for WLAN (11bit, 10MHz BW). I don't have monte-carlo simulations, only measurments.
But, I agree that you can't compare that directly with ycm's specs.

YCM: Choosing the delta-sigma modulator topology, OSR, sampling fequency etc. isn't a random process, but rather a careful analysis of pros and cons. You can design the best amplifiers, if you decision at system level were bad you will never get a good circuit.

Regards

Title: Re: high oversampling ratio
Post by ycm on Aug 15^th, 2009, 9:14pm

Hi Sumit,

I am going to use Matlab to run some simulations first. By the way, if I use a second order single bit modulator followed for a sinc3 filter, (fin bandwidth=1kHz, OSR=1024, 16bit resolution) what is the total conversion time for the ADC? my understanding here is sinc3 filter needs N taps and N must be equal to OSR, so the delay of the filter is OSR which is equal to OSR*Tclk=Tinputsignal/2=1ms/2=0.5ms, is that correct? if that is correct, does not that mean the conversion time is always equal to half of the 1/fin without any relations with 16 bit resolution?

also, how to explain the output of sinc3 filter? say if the inputs to ADC are 1/2, 1/4, 1/8 of full scale and ADC is 16 bit, sinc3 filter outputs are y(1), y(2), y(3) ...., how to explain y(1), y(2), y(3) ....? my understanding y(1)='00FF'H, y(2)='000F'H, y(3)='0003'H, is that correct?

Thanks a lot

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 15^th, 2009, 11:43pm

Hi YCM,
Please find my replies inline.

Hi Sumit,

I am going to use Matlab to run some simulations first.

>> Judicious. Use Matlab to find out the frequency response of entire
signal chain. Also analyze pole-zero plot for your SDM and settling
time for each block and entire signal chain. Optimize you SDM
topology by choosing proper coefficients.

By the way, if I use a second order single bit modulator followed for a sinc3 filter, (fin bandwidth=1kHz, OSR=1024, 16bit resolution) what is the total conversion time for the ADC? my understanding here is sinc3 filter needs N taps and N must be equal to OSR, so the delay of the filter is OSR which is equal to OSR*Tclk=Tinputsignal/2=1ms/2=0.5ms, is that correct? if that is correct, does not that mean the conversion time is always equal to half of the 1/fin without any relations with 16 bit resolution?

>> Well there are two things here. First is the group delay.
I your case it will be 3/2 cycle of downsampled clock(third order
CIC). It means 1ms*3/2 = 1.5 ms (at the output of CIC). The
answer changes if you have chopping/dechopping. In that case
CIC schemes will be different. Important to know about chopping.
I wont like non-integral delays anyway. I would have been
compensated it for 2 delays (not 3/2 delays).

Second is settling time. Means if suddenly input changes (say
from 0 to full scale, step input). Do a step response analysis in
Matlab on CIC or entire filter chain.

Please do a Monte Carlo Simulation on Matlab over pole zero and
frequency response to see the stability of your system.
Your integrator response will be somehow as follows :

H(z) = beta*z^-1/(1 - alpha*z^-1)
where beta = Cs/Cf
and alpha = 1.0 - beta/Aol (Aol = open loop gain of OPAMP)
beta is the gain of integrator and alpha is leakage.

vary Cs and Cf with a normal random number and plot response
and pole-zero plot of entire SDM. This will tell you about pole
spread and system response (by this term I mean both STF and
NTF), which in terns helps you determine the sizes of Cs and Cf

1ms *

also, how to explain the output of sinc3 filter? say if the inputs to ADC are 1/2, 1/4, 1/8 of full scale and ADC is 16 bit, sinc3 filter outputs are y(1), y(2), y(3) ...., how to explain y(1), y(2), y(3) ....? my understanding y(1)='00FF'H, y(2)='000F'H, y(3)='0003'H, is that correct?

>>> You know the answer partially. The answer is hidden in DNL and
INL requirements of an ADC. at zero input output has to be
0 and at full scale it would be 65535 (if you use unsigned
arithmetic, Note this is very important to select the arithmetic of
DSP. It helps reducing your current consumption. Example
signed arithmetic is good for upto 8 bits of registered width,
but for you it would be unsigned 2's complement as your bitwidth
will be 16 or more bits. Please refer Anantha Chandrakashan
for better understanding,
http://www-mtl.mit.edu/~anantha/publications.html).
Accordingly common mode(1/2) will be
32768. There is an issue here. You need to check your CIC gain
here. For example if you use CIC of DSR 64, the output gain
(D.C) will be around 108.37 dB. So you can achieve with 16 bits
output as 108.37 - 2*6 = 96.37 dB, which wont be 16 bits. This
is intrinsic characteristic of CIC. One example to fix this is
calibration coefficients.

If you are using a straight FIR implementation then for sinc3
filter u need N coefficients. That same filter can be reduced to
a CIC response, there u need 6 taps only :).
for 1024 down sample 1024 tap FIR is simply too large to
implement. So better to use its CIC reduced form :)

Thanks a lot
>>> You are always welcome :)

Title: Re: high oversampling ratio
Post by ycm on Aug 16^th, 2009, 8:23am

wow, so detailed answers. :)

The conversion rate is only related with 1/finput signal bandwidth and has nothing to do with OSR. But how about the group delay? if there are 2 delays in sinc3 filter, the conversion for one input signal will be 2ms which does not meet the 1ms conversion time requirement. How to solve this problem to meet 1ms conversion time spec? >:(

Maybe the way to increase the input signal bandwidth to 2kHz so the delay will be 3/(2fin)=3/(2*2k)=0.75ms, the conversion time is 0.75ms, is that correct way to do?

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 16^th, 2009, 10:10pm

Possible. Following is a scheme.
| SDM(2MHz) | ----> | CIC1, 3rd order, DSR = 512 | ---> | CIC2, 1st order, DSR = 4 | --->

CIC1's output has 0.5 ms delay.
CIC2 : First order. Use delay free integrator and unregistered downsampler output, then
only group delay comes from one differentiator (1/2 delay) , so the delay introduced
by this block is 0.5 ms.
So total delay 0.5ms + 0.5 ms = 1 ms.

There are so many other combinations possible.
I already gave answers for group delay (how 3/2 delays are coming). here also we matched group delays.
BTW, What is ur frequency response spec ?

Title: Re: high oversampling ratio
Post by ycm on Aug 17^th, 2009, 7:48am

if the DR of the first CIC and second CIC are 512 and 4, then OSR is going to be 512*4=2048, since fs is 2MHz, so the input signal bandwidth is around 0.5kHz instead of 1kHz? thanks

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 17^th, 2009, 8:40am

Output Sampling rate = 2MHz/(4*512) = 1kHz and the BW = 500 Hz. I thought that u need output sampling rate of 1 kHz! I am sorry for
wrong understanding.

Following could be one of ur scheme.
| SDM(1MHz) | ----> | CIC1, 3rd order, DSR = 512 | -->
Output Delay = 0.5ms + 0.5 ms = 1ms, rate = 1024/512 = 2kHz.
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 17^th, 2009, 9:10am

If the DR of the second CIC is changed to 2, all the other conditions are the same, the delay of the the first CIC is still 2 cycle latency=0.5ms and the the delay of the second CIC is 0.25ms so the total is 0.75ms, is that correct? thanks

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 17^th, 2009, 9:38am

No need to add CIC2
| SDM(1MHz) | ----> | CIC1, 3rd order, DSR = 512 | -->
Output Delay = 0.5ms + 0.5 ms = 1ms, rate = 1024/512 = 2kHz.
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 17^th, 2009, 9:53am

sinc3 filter always introduce 2 cycle delay, so the conversion time is equal to 2*1/fdatarate=2*1/2kHz=1ms, right? :)

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 17^th, 2009, 9:56am

Thats what you wanted. U asked to meet the spec of conversion delay of 1ms

"The conversion rate is only related with 1/finput signal bandwidth and has nothing to do with OSR. But how about the group delay? if there are 2 delays in sinc3 filter, the conversion for one input signal will be 2ms which does not meet the 1ms conversion time requirement. How to solve this problem to meet 1ms conversion time spec? Angry"

BR,
Sumit

Title: Re: high oversampling ratio
Post by ycm on Aug 17^th, 2009, 9:58am

Sumit Adhikari wrote on Aug 17^th, 2009, 9:38am:

No need to add CIC2
| SDM(1MHz) | ----> | CIC1, 3rd order, DSR = 512 | -->
Output Delay = 0.5ms + 0.5 ms = 1ms, rate = 1024/512 = 2kHz.
Sumit

now for input signal bandwidth 1kHz, OSR=512, for your past design experience, the silicon came back can achieve 16 bit accuracy? how small the power supply voltage for single power supply could be to achieve this accuracy for 1kHz bandwidth with 512 OSR? thanks a lot. :)

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 17^th, 2009, 10:38am

Should not be a problem. I have seen it working with lesser DSR ;)

I design for automotive. I have limited experience on various supply
options. You can definitely make it working from 2.8V to 3.5V supply
range.

My modeling says that you should not have problem upto 1.8 volts,
provided you choose proper architecture. But no silicon data for this.

I would suggest u to keep trimming options open and explored for all
supporting analog blocks. Be worried about your buffer/PGA

Keep an eye on 1/f noise. That will be killer.

Regards,
Sumit

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 17^th, 2009, 11:51pm

Just checked with my models. It should work with 3.3 volts supply.
what is ur supply voltage ?

BTW, Do u have a droop correction ?

Title: Re: high oversampling ratio
Post by ycm on Aug 19^th, 2009, 6:58am

I plan to have a low vdd. 1.8v would be nice;

Drop compensation is usually done in the digital sinc3 filter? does that introduce extra delays? Using sinc3 filter to down sample directly with the decimation factor 512, do we need to implement for several stages?

Also the circuit must be implemented in full differential in practical?

I could not see your attachment in gmail. could you send it again? thanks.

Title: Re: high oversampling ratio
Post by Sumit Adhikari on Aug 20^th, 2009, 11:59pm

Hello YCM,
Sorry for the delayed response. I was busy with reviewing some designs.
After receiving this mail from you , I think you don't have any spec with you. I would like to know the application. 1.8 Volts gives me a feeling that
you want to design for audio application. Am I correct ?. This sounds like a student project.

Droop compensation comes when you want a clean frequency response of the system designed by you. The CIC introduces a droop at and around
band edge of the frequency response of your system. That can be corrected a FIR filter. Generally a droop correction FIR filter has high number
of coefficients (20 or higher). So obviously you will be having more conversion delay as FIR is generally last stage and operates at the lowest
sampling in your DSP. The use of such an FIR is also desired to improve your stop-band attenuation (as CIC dosent have a very good stop-band
attenuation).

If you want to get rid of your common mode noise then it must be implemented as fully differential circuit. However, you can analyze your system
as single ended. Fully differential in system level doesn't have much impact.

Well chopper wont be there in sigma delta ADC. It will be at the input of your system, even before your buffer/PGA. It can be implemented using
a pair of switches. You need to find out your chopping frequency/rate, this depends on your output bandwidth/sampling rate. Depending on that
you will have to plan the bandwidth of each blocks in your system. Typically people obeys a thumb rule as any block after chopper will have a bandwidth
of 10-15 times the chopping frequency. I maintain it 20 times. The chopper frequency has to be at least 2 times your output sampling rate (downsampled
rate). Some people keeps it as their output sampling. Chopping is kind of a modulation and demodulation technique with the synchronization in mind (
delay matching in DSP). Your DSP needs to dechop the signal. The plan for such chopping/dechopping technique requires a seperate plan for your dsp.
The CIC needs to be divided into at least two parts and the dechopping needs to be done after first CIC. The selection of first CIC is critical. It needs
to have a lower DSR (it means fast settling time) to accommodate chop clock. By chopping you force the dc and 1/f noise to be thrown out to the
chopper frequency and this dc/(1/f) will be removed by the second CIC. Implementation of Chopper/dechopper requires some relaxed conversion rate
and your plan from sigma path needs to be well reviewed.

BR,
Sumit