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Simulators >> RF Simulators >> comparator noise simulation
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Message started by aaron_do on Aug 17^th, 2009, 12:30am

Title: comparator noise simulation
Post by aaron_do on Aug 17^th, 2009, 12:30am

Hi all,

i'm guessing this has been asked before, but i'm wondering how do I simulate the input-referred noise of a comparator. Assume that the clk frequency is 1 MHz. The method I used was to run a PSS and Pnoise analysis and check the 0th sideband of the pnoise analysis. I then integrated the noise over the bandwidth from 1 kHz to 1 GHz...Is this method correct? I'm basically trying to find what bit resolution this comparator can be used up to.

One more thing, should I be only integrating the noise up to the clock frequency?

thanks,
Aaron

Title: Re: comparator noise simulation
Post by aaron_do on Aug 17^th, 2009, 10:32pm

Hi all,

so this is what i eventually did. Please comment on whether this method is good or bad. I used a transient noise simulation which ran for 40 clock cycles with a square wave input. I did altogether 250 runs which results in a total of 10000 samples. Of the 10000 samples, I found there to be 2 bit errors when the input voltage was 1 mVpk, so for 1 Vpk maximum signal swing, I can say that the BER is approximately 1/5000 with log(1/0.001)/log2 = 10 bit accuracy. The actual input-referred noise is of secondary importance since we are more concerned with the BER. For accuracy I believe I should have enough runs for about 30 errors or so...

Does this all sound right? I have a feeling I didn't calculate the bit accuracy properly.

cheers,
Aaron

Title: Re: comparator noise simulation
Post by Sumanjit on Aug 24^th, 2009, 11:04am

I believe that comparator noise simulation and BER are two different things.

To do the BER simulations you should read this paper from cadence http://www.designers-guide.org/Analysis/metastability.pdf

As for the noise simulations i am also trying to find a solution for it. I will keep you posted if i come up with anything useful.