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Design >> RF Design >> tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design
https://designers-guide.org/forum/YaBB.pl?num=1250675225

Message started by Read_MLY on Aug 19^th, 2009, 2:47am

Title: tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design
Post by Read_MLY on Aug 19^th, 2009, 2:47am

hi all,

now, I am designing a cmos vco which works at 8Ghz(highest freq, wideband),using TSMC 0.13um cmos process.but I don't use this process before,so I now don't make sure how much parasitical capcitance I need to consider,who can help me?

thanks

Title: Re: tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design
Post by macrohan on Sep 22^nd, 2009, 6:13pm

If you consider the parasiticl capcitance, especially layout parasitical capcitance, in my design option, may be 400~500fF parasitical cap that you must consider before desiging.

Title: Re: tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design
Post by Riad KACED on Oct 23^rd, 2009, 10:34am

Hi Macrohan,

You better look at TSMC's Design Rule Manual. Besides, the TSMC 0.13u comes with various metal options. Needless to remind you that different metals have different parasitic caps.
You may just draw some lines and extract them using Calibre/Assura, this gives you a rough idea.

Cheers,
Riad.

Title: Re: tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design
Post by duncandu on Oct 24^th, 2009, 10:11am

ReadWDX wrote on Aug 19^th, 2009, 2:47am:

I personally suggest that you just design it and get some feelings. In fact, 8G Hz is not that high for .13um process, and I guess you still need to add MIM caps into the resonant, so that even though you find the parasitic cap is large in post simulation, you can simply decrease some MIM caps.

Title: Re: tsmc 0.13um process parasitical capacitance when 8GHz CMOS VCO design
Post by Mayank on Nov 3^rd, 2009, 7:19am

Hello Read_MLY,
First, estimate the routing length that you will require to route your oscillator nodes...Estimate it depending upon :---
1. No. of stages in your Oscillator
2. Size of transistors used in each stage.
3. a Rough Idea of How you are going to place your stages in layout...

These points may give you a fair idea of the length of each oscillator node....

Then simply draw a metal lines of the required width & length as Riad said, and extract Post-layout netlist of that wire to get a rough idea of routing cap...

Proceed with schematic design by placing a cap of around that value(somewhat higher) at each oscillator node....

--mayank.