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Design Languages >> Verilog-AMS >> case statement in verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1250851965

Message started by rajdeep on Aug 21^st, 2009, 3:52am

Title: case statement in verilog-A
Post by rajdeep on Aug 21^st, 2009, 3:52am

Hi all,

How will spectre simulate case statement in Verilog-A?

case(sum)
0: vnom = 1.2;
1: vnom = 2.3;
endcase
In the above example will the entire section be simulated at every time point or will it be intelligent enough to simulate the section only when there is a change in sum??

Im curious because what if I have the following statement in conjunction with the above statement..

V(vout,gnd) <+ transition(vnom,td,tr);

If spectre evaluates vnom at every timepoint then the argument of transition will be evaluated at every time point. Wont it slow down the sim unnecessarily?

I have tried to wrap up the case statement within a cross statement just to experiment and frankly speaking there was absolutely no difference!!! But that could be because of the simplicity of the testbench...any thoughts?

Thanks much!
Rajdeep

Title: Re: case statement in verilog-A
Post by Geoffrey_Coram on Aug 21^st, 2009, 12:56pm

You might want to read through this thread:

http://www.designers-guide.org/Forum/YaBB.pl?num=1220537539/0#0

It looks like you picked a formulation that is similar to the faster of the two approaches mentioned.

Title: Re: case statement in verilog-A
Post by Sumit Adhikari on Aug 22^nd, 2009, 8:24pm

It wont work. There is no tigger for the case statement.
Write is as follows :

always @(*)
case(sum)
0: vnom = 1.2;
1: vnom = 2.3;
endcase

Further it will give u an error as you are using vnom in analog block
and it is not initialize. Initialize it. Following could be a nice approach:

always @(*)
case(sum)
0: vnom = 1.2;
1: vnom = 2.3;
default : vnom = (whatever_value_you_choose);
endcase

Regards,
Sumit

Title: Re: case statement in verilog-A
Post by Geoffrey_Coram on Aug 24^th, 2009, 4:46am

Sumit -
I think rajdeep was intending for the case statement to be in the analog block also, along with the transition, in which case the trigger is not needed.

Title: Re: case statement in verilog-A
Post by rajdeep on Aug 27^th, 2009, 6:07am

Hi Geoffrey!

Thanks for the link! I remember to go thru that thread once before!! So, I guess the conclusion is to make vnom change only when sum changes i.e. wrap the case statement within a cross statement. This will make the transition filter work faster!

@Sumit: Im using Verilog-A, not Verilog-AMS. Sorry for the confusion!

Rajdeep