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Design Languages >> Verilog-AMS >> discipline phase problem
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Message started by bandpass on Sep 8^th, 2009, 5:50am

Title: discipline phase problem
Post by bandpass on Sep 8^th, 2009, 5:50am

I use the model from kundert's paper, which declare the discipline phase, but when I simulate in Hspice, it's error. The error information is:Discipline compatibility at 'clkin': disciplines 'electrical' and 'phase' are incompatible.

I add the following three lines to disciplines.h

discipline phase
potential Angle;
enddiscipline

The veriloga module is:

`include "disciplines.h"

`include "constants.h"

//`include "phase.vams" // from Listing 2, includes disciplines.vams.

module divider(in, out);

input in; output out;

phase in, out;

parameter real ratio = 1 from (0:inf); // divide ratio

parameter real n = 0 from [0:inf); // white output phase noise (rads2/Hz)

parameter real fc = 0 from [0:inf); // flicker noise corner frequency (Hz)

analog begin

Theta(out) <+ Theta(in) / ratio;

Theta(out) <+ white_noise(n, "wpn") + flicker_noise(n*fc, 1, "fpn");

end

endmodule

Title: Re: discipline phase problem
Post by Ken Kundert on Sep 8^th, 2009, 11:06am

The problem is probably due to what you are connecting to the divider. Apparently you are trying to connect an electrical component to a phase port.

-Ken

Title: Re: discipline phase problem
Post by bandpass on Sep 9^th, 2009, 5:57am

Ken Kundert wrote on Sep 8^th, 2009, 11:06am:

The problem is probably due to what you are connecting to the divider. Apparently you are trying to connect an electrical component to a phase port.

-Ken

Thanks for your reply. I still have some questions about the simulation of phase-domain model of PLL. The models are from your paper. The question are:
(1)As you know, when we do AC simulation, we should specify the stimulate source for ac, but as your model metioned, the port are phase type, which cannot be descibe by V** I**. how can I describe the phase source in netlist?
(2) In your mode, the top netlist mode is pll.va, which has no input source, just use the oscillator as input. when we simulate the testbench, the PLL just has one phase output port, has no input port, so the AC simulation will not take effect.

What's your suggestion? thank you very much

The attachment is the Hspice testbench of PLL phase domain model. The top netlist is as follows:

***phase domain simulation
.TEMP 25.0
.OPTION
*+ ARTIST=2
+ INGOLD=2
+ MEASOUT=1
+ PARHIER=LOCAL
*+ PSF=2
*.options probe
+ post=1
+ delmax=1e-10

.hdl "oscillator.va"
.hdl "divider.va"
.hdl "oscillator.va"
.hdl "phaseDetector.va"
.hdl "pll.va"
.hdl "vco.va"
.hdl "loopFilter.va"
xpll out pll

.AC DEC 10 1 1MEG
v1 clkin 0 AC 1 *PULSE 0 1.2 0 1e-9 1e-9 9e-9 20e-9

.end

Title: Re: discipline phase problem
Post by Ken Kundert on Sep 9^th, 2009, 1:11pm

You would create a phase source using Verilog-A.

-Ken

Title: Re: discipline phase problem
Post by Geoffrey_Coram on Sep 14^th, 2009, 6:16am

bandpass wrote on Sep 9^th, 2009, 5:57am:

[color=#0000ff]
(1)As you know, when we do AC simulation, we should specify the stimulate source for ac, but as your model metioned, the port are phase type, which cannot be descibe by V** I**. how can I describe the phase source in netlist?

Perhaps you knew this, but instead of V, the potential access function for discipline phase is Theta; you haven't declared the flow nature, which you would need to be able to access the flow.