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Design Languages >> Verilog-AMS >> Phase noise to jittter in verilogA
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Message started by nandy on Sep 9^th, 2009, 5:38am

Title: Phase noise to jittter in verilogA
Post by nandy on Sep 9^th, 2009, 5:38am

Hi

I have simulated pss and pnoise of a VCO and have extracted a table of its phase noise vs frequency in dBc/Hz. Now I need to estimate how much jitter this contributes to a PLL loop. For this I have a PLL loop with ideal elements, but I want the ideal VCO block to take the phase noise table of the actual VCO as its input and produce the corresponding jitter at its output. How do I do it? Can I do it using VerilogA?

Title: Re: Phase noise to jittter in verilogA
Post by ywguo on Oct 7^th, 2009, 7:38am

Hi nandy,

Calculate the integrated phase noise based on the extracted table of VCO phase noise. Given it is dominated by white noise, the integrated phase noise is the rms jitter of VCO output. The unit is degree or radian now. Convert the unit to second. Describe your VCO with the rms jitter and do transient simulation.

Probably the rms jitter is too small to be detectable in the transient simulation. :( Personally I prefer an analytical model to derive the rms jitter of the PLL output.

Best Regards,
Yawei