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Design >> Mixed-Signal Design >> What is drawback to use minimum-sized transistors for analog switch?
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Message started by tony_taoyh on Sep 16^th, 2009, 4:11am

Title: What is drawback to use minimum-sized transistors for analog switch?
Post by tony_taoyh on Sep 16^th, 2009, 4:11am

To reduce the charge injection and clock feed-through for analog switch,

minimum sized device can be used if Ron is not a issue.

What is the drawback to use the minimum sized device?

Thanks a lot.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by Berti on Sep 16^th, 2009, 4:16am

If settling (Ron, also taking into account process variations) is still ok I don't see an issue.

Other opinions?

Regards

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by raja.cedt on Sep 17^th, 2009, 12:13am

hi,
what is the meaning of no issue Ron? means if you have any value is it ok or even though it changes with time or PVT? because if you put smaller switch you will see larger PVT variations

Thanks,
Rajasekhar.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by Mayank on Sep 17^th, 2009, 1:16am

hi,
minimum sized device(or length) will introduce more flicker noise....That might cause problems.

regards,
Mayank.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by raja.cedt on Sep 17^th, 2009, 3:53am

hi,
ya,thats true but generally in high speed sample and hold circuits flicker noise will not come due to its low frequency spectrum. By the where you are using switch?

Thanks,
Rajasekhar.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by RobG on Sep 17^th, 2009, 8:39am

I think it is one of those rules of thumb that has been followed so long nobody can remember why. The reason I was given was that you are pushing the edge of the process, which might give some leakage when off, but I'm not sure how true this is. I used min gate lengths for my last design.

You may already know this, but contrary to intuition, differential charge injection is minimized with minimal switches since you are subtracting the mismatch, not averaging the mismatch. So that is another reason to use as small as possible switches.

rg

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by raja.cedt on Sep 17^th, 2009, 10:05pm

hi rg,
i didn't understand last para in your post (average mismatch....etc)...if you decrease the device size all secondary effects will decrease vth and leakage will increase. And i feel differential configuration would be help full to cancel this one.

Thanks,
Rajasekhar.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by Berti on Sep 18^th, 2009, 12:11am

rg, I don't understand your post, too. What "rules of thumb" are you talking about?

Rajasehkhar, "decrease the device size" means decreasing L or W? Why decreases vth with smaller W?

Cheers

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by tony_taoyh on Sep 18^th, 2009, 12:54am

Thanks a lot. Guys.

With short channel effect, the Vth is roll-off when L is reduced.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by raja.cedt on Sep 18^th, 2009, 1:30am

hi berthi,
i am sorry, type mistake decreasing w will increase Vth due narrow width effect

Thanks,
Rajasekhar.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by Berti on Sep 18^th, 2009, 5:10am

Rajasekhar, sorry, I think you original post was generally correct (in fact I think it depends on the technology, but I am not so familiar with this topic).

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by rajdeep on Sep 18^th, 2009, 7:29am

Hi all,

I also think it is due to more PVT variation at min length. The models that we use for simulaiton may not be that accurate at that limit. It is always safe to use 4*Lmin if possible. So, if speed is ok and feedthrough problem doesnt increase much I'll tend to use longer length just to be in the safer side.

Not sure whether the switch will be more leaky or not in OFF state when using Lmin for the same W/L ratio...... :-X

Thanks,
Rajdeep

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by RobG on Sep 18^th, 2009, 8:08am

Berti wrote on Sep 18^th, 2009, 12:11am:

rg, I don't understand your post, too. What "rules of thumb" are you talking about?

I was speaking about the "rule of thumb" that says not to use minimum sized devices for switches. Throughout my career I've heard it from many people to use channel lengths a bit longer than minimum, but nobody ever knew exactly why.

As dimensions decrease the Vt starts changing pretty rapidly with small ΔL and ΔW implying more mismatch potential. Perhaps that is a practical consideration.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by RobG on Sep 18^th, 2009, 8:30am

raja.cedt wrote on Sep 17^th, 2009, 10:05pm:

Guess I'm confusing everyone...

I was talking talking about charge injection in differential circuits. As you know, if it is matched the injected charge is common mode and not an issue.

On the other hand, if there is a mismatch in the injected charge you will get an error signal. It follows that you would like to match the charge injections as well as possible. Most people assume that larger switches will match better, but this is not true for matching charge injection. The matching improves as sqrt(area), but the amount of charge increase proportional to area.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Sep 19^th, 2009, 4:17pm

Common mode effects are greatly reduced, agreed, but not eliminated. Don't get into binary thinking ;) with analog systems.

From my experience, min geometry for switches is generally the way to go. For everything else, the matching concerns and PVT variance come out to bite you.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by Berti on Sep 20^th, 2009, 10:37pm

Quote:

It is always safe to use 4*Lmin if possible.

That's true, but you won't be able to design highest-performance circuit with such a conservative approach.

Cheers

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by MarcoC on Sep 21^st, 2009, 1:01am

Hi guys,
I'm very interested about his topic but all of these posts have made me a little bit confused. :-/
Which is the better choiche???
It is better to use minimum sized devices or not?
Moreover, in case I would minimize the charge injection, which is the better choice?

Regards,
MC

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by ywguo on Sep 21^st, 2009, 1:52am

Hi MC,

Quote:

Which is the better choiche???
It is better to use minimum sized devices or not?

Assume the model is accurate, I think it depends on your design.

Quote:

Moreover, in case I would minimize the charge injection, which is the better choice?

I will choose the minimum sized MOS transistors for this case.

Best regards,
Yawei

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Oct 4^th, 2009, 3:04pm

Also, to minimize charge injection, in addition to minimum geometry, you should be using a charge compensated switch, and a restricted gate voltage swing, and....

Time to open a book on switched capacitor circuit design.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by vivkr on Oct 5^th, 2009, 2:20am

Let me add my bit:

1. I would use a minimum-channel length: There is a clear metric for designing switches which says that Ron*Qinj = k/Lchannel^2, i.e. realizing a switch with a desired resistance level and a minimum possible charge-injection requires minimizing channel length. Look up your Razavi or work it out by hand.

2. In my opinion, it is far better to avoid loading your sensitive nodes with additional dummy switches in an attempt to "cancel" charge-injection. This works only at zero-order assuming the dummy switches really soak up the correct amount of charge, which is a very complex function of the risetimes, impedances seen in both directions by the switch etc. This works better for clock feedthrough and less for charge-injection.

3. Unless there is some very specific requirement for low "absolute error" due to charge-injection as in some high-precision sensor, or your technology is really lousy (in which case dummy switches are probably also lousy), I would simply worry about avoiding "signal-dependent charge-injection" and forget about fixed charge-injection. Use bottom-plate sampling (a delayed clock phase to open the signal-dependent floating switches), and a differential architecture for your circuit. The above scheme is like taking an aspirin for a headache. There may be several causes and/or effects but in most cases, your headache will be cured (not my own).

4. If on the other hand, you really want to know more about charge injection, then there are papers by Eric Vittoz and his student George Wegmann (look up old JSSC). There are also several other circuit techniques which supposedly reduce charge injection, but most provide only a limited benefit for large costs. One such example that I can recall is where the authors used a switched opamp instead a switch. The reasoning was that the opamps output stage which is acting as a switch has transistors in saturation (channel pinched off near the drain), and so when they are turned OFF, then the charge flows towards the source end and you have less charge injection. As you can guess, there are very many conditions that need to be met for this scheme to really work well, plus you have an opamp for each switch.

5. Boosting the gate (or a fixed gate-source overdrive) may provide a more signal-independent charge injection level but would barely suffice on its own (on top of being a more complex scheme). I would stick with bottom plate sampling as I mentioned above.

Regards,

Vivek

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Oct 6^th, 2009, 11:22pm

As with many engineering decisions, this is one where you are going to have multiple solutions, and several solutions that all work well. Charge compensated switches are generally not used at high frequencies (excessive capacative loading yes..) but is still commonly used for lower frequency sampling systems in order to keep the holding capacitor sizes smaller.

However simulations of these things are often misleading due to inaccurate transistor models, the usual methodology is 4 transistors, two in parallel as the switch, and one on each of the drain/source as a dummy driving capacitance, with complementary gate signals. (All 4 transistors have the same geometry) The methodology has been in used for quite a while.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by vivkr on Oct 13^th, 2009, 1:36am

loose-electron wrote on Oct 6^th, 2009, 11:22pm:

agree fairly with you Jerry, but a couple of points:

1. While transistor models may not be very accurate, they are getting better all the time, and a mature process may not have such bad models. In any case, the local impedances at source/drain may be more important than unmodelled NQS effects in most cases => better sim accuracy.

2. I found dummies to be of limited use while working on 20bit, 100 kHz systems. They are huge (dummy switches as big as main switch), and although speed is low, so is the power budget (and managers with knowlege of the inverter power consumption CV^2f think that systems at a few kHz should anyway need zero power, since their Excel sheet shows frequency in GHz to 2 digits after decimal :). My point is that you can probably do better than using dummies, unless you are making uncalibrated absolute-accurate incremental ADCs.

3. You mention adding 4 transistors, 2 as the pass gate (1 P + 1 N I assume), but surely you also need a P and an N on either side to do the charge cancellation with the dummy, and would have 6 transistors that way.

Regards,

Vivek

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by jiesteve on Oct 14^th, 2009, 12:25am

Jerry,

Why is the switch implemented as two parallel devices?

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Oct 16^th, 2009, 10:52am

The use of 2 transistors in parallel is a modeling trick, all 4 transistors are exact same geometry, and that way the charge cancellation is (in theory, and this is a time to NOT trust simulation results!) balanced.

The switch I was describing (with 4 transistors) is a PMOS only or NMOS only structure. If you want wide range (NMOS with PMOS pass gate) then it gets even messier with a total of 8 transistors in the switch.

Generally I would not go there.

As for models getting better? Sorry, but I strongly disagree and agree at the same time. Almost always models lag silicon by a generation or two (or three or...) and the "chicken and egg" analogy (which comes first) applies.

Also, almost all models the parameters are not properly set for specific items that are extremely difficult to measure and this includes the charge holding capacitors that are non-linear(junction depletion capacitance of drains and sources come to mind, as well as channel inversion charges) as a rule these are not set properly.

As well a cautionary comment - Just because a foundry claims they have the "latest and greatest BSIMX.X" models does not really mean much. I have done foundry model audits and when you get inside the details of the model you find that 80% of the parameters are not set properly (or at the default value) and what you really have is a much older and simpler model due to the fact that the they never used most of the parameters in the transistor model.

Jerry

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Oct 16^th, 2009, 10:58am

Here take a look at these:
]
http://www.effectiveelectrons.com/Spice1.htm

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by schen on Oct 16^th, 2009, 11:23am

Mismatch with min L switchs is bigger although charge injected might be not as bigger as mismatched area in ratio sense. I think one should do careful simulation to find an optimized L for given frequency. Min L might not be optimized value. Min L causes bigger leakage and it will cause bigger error. For higher frequency sampling clock it may force you to use Min L. If frequency not high, it is better to use bigger L than min L, mismatch is smaller and PVT effect is smaller.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by jiesteve on Oct 19^th, 2009, 5:35pm

Hi Jerry,

Could you please post the schematic and/or layout of the 4 transistor scheme... I'm not quite following what is going on.

Thanks!

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Oct 20^th, 2009, 8:10am

Here you go -

Important note - the Top transistor is 2 devices in parallel - and there are a total of 4 transistors all the same size.

The gate control for the bottom pair of transistors is the complement of the gate control that drives the top two transistors.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by jiesteve on Oct 20^th, 2009, 8:16pm

OK, this is making sense now. Thanks.

Title: Re: What is drawback to use minimum-sized transistors for analog switch?
Post by loose-electron on Oct 22^nd, 2009, 9:02am

Not a problem - this has been around for a while - - since at least 1980 - look at the schematic it was drawn when 0.6 micron transistors were state of the art.