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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Logical Behaviour for VerilogA https://designers-guide.org/forum/YaBB.pl?num=1253116314 Message started by eddie on Sep 16th, 2009, 8:51am |
Title: Logical Behaviour for VerilogA Post by eddie on Sep 16th, 2009, 8:51am Hi. I admit it, I'm new to VerilogA. I need a resistor in which the resistance changes depending on the voltage. So a simple resistor is: module res(p,n); inout p,n; electrical p,n; parameter real r=0 from [0:inf); analog V(p,n) <+ r*I(p,n); endmodule I have a set of voltage threshold values and resistances that are defined at the top of my code (`define etc), basically a set of linear approximations to an exponential increase in resistance with voltage. So I have: if (V(p,n) < VD2) Resistance = RA else if etc, where RA and VD2 are both defined in the file above. Can anyone tell me why I get a syntax error in the if statement, already looked up if statements in the VerilogA Reference Manual. Is it that the values VD2 etc are not actually physically relevant (i.e. not actual voltages etc) The error I get is: line 26: "if <<--? (V(p,n) <= VD2)" line 26: Error: syntax error How would you change the resistance of a resistor with voltage, temperature etc. Thanks. Ed Fisher |
Title: Re: Logical Behaviour for VerilogA Post by Ken Kundert on Sep 16th, 2009, 11:31am There are two issues. The first is how to write a model that compiles. This would probably be a pretty easy question to answer if you actually gave your model. The second is a more subtle issue on how to model resistors. Just like with capacitors, it is important to formulate the model to avoid charge conservations problems. These occur if you calculate the resistance as a function of voltage, and then describe the model with i=v/r(v). Instead, if you have resistance as a function of voltage, you must recognize that r = dv/di and integrate ∫r di = ∫ dv to get v as a function of i and then write the model using that function. This process is described for capacitors in http://www.designers-guide.org/Modeling/varactors.pdf. -Ken |
Title: Re: Logical Behaviour for VerilogA Post by eddie on Sep 17th, 2009, 6:21am Ok so I worked through the maths for a voltage dependent resistor. That should work quite well but in this case all I need to do is conditionally change the resistance of the linear resistor model depending on where in the SPAD (single photon avalanche diode) reverse breakdown region it is operating. So now back to a syntax problem, ironically I'm getting errors when some of the syntax is exactly the same as the Varactor Verilog-A model that is referenced above. Here is my model; `include "disciplines.vams" module Rspad(anode, cathode); inout anode, cathode; electrical anode, cathode; parameter real R0 = 1k from (0:inf) //zero bias Rspad resistance real v, r; //define variables used for calculation analog begin v = V(anode, cathode); //get voltage over component r = R0; //not used for calculation //used for logical decision only if (v <= `V2) //conditional assignment of r r = `RA; //voltage dependant else if (v <= `V3) r = `RB; else if (v <= `V4) r = `RC; else if (v <= `V5) r = `RD; else r = `RE; V(anode, cathode) = r*I(anode, cathode); //calculate voltage end end module So I get a number of syntax errors, the first is: line 67: "real <<--? v, r;" line 67: Error: syntax error line 67: Error: illegal declaration line 67: Error: parameter "r" requires initializer line 70: "v <<--? = V(anode, cathode);" line 70: Error: undeclared symbol: v. Any help would be much appreciated. Also is y=`x the correct way if x is defined using `define x 2; Thanks very much. Ed Fisher |
Title: Re: Logical Behaviour for VerilogA Post by Geoffrey_Coram on Sep 17th, 2009, 9:51am eddie wrote on Sep 17th, 2009, 6:21am:
This line need a semicolon after the range: from (0:inf); I think the compiler errors are consistent with this (rather than you having left it off as you copied the model to the forum). |
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