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Design >> Analog Design >> Low offset, high speed CMOS comparator
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Message started by jiesteve on Sep 17^th, 2009, 11:21am

Title: Low offset, high speed CMOS comparator
Post by jiesteve on Sep 17^th, 2009, 11:21am

I need to design a high speed comparator with input referred offset < 1.8mV, 3sigma. What sort of topologies should I be looking at? Do I need to do offset cancellation? VDD is 1.8V.

Title: Re: Low offset, high speed CMOS comparator
Post by thechopper on Sep 17^th, 2009, 7:18pm

Hi,

First of all I think I would use a pre amp stage to minimize offset contribution from the decision ckt.
Even in that case the total input referred offset might be larger than what you need to achieve.
So offset cancellation technique like chopping or autozeroing may be necessary (making your preamp diff pair with very large devices to minimize offset might impact your comparator speed).
Autozeroing might be more convenient if your comparator is clocked, unless input referred noise is an issue (aliasing related to autozeroing).
Obviously chopping is the other option.

Regards
Tosei

Title: Re: Low offset, high speed CMOS comparator
Post by raja.cedt on Sep 17^th, 2009, 8:55pm

hi,
first design high speed comparator and don't consider offset and then nullify offset using digital calibration (it is much better than other analog cancellation techniques from tuning point of view)

Thanks,
Rajasekhar.

Title: Re: Low offset, high speed CMOS comparator
Post by rajdeep on Sep 18^th, 2009, 8:19am

Hi Rajsekhar,

Can you please suggest any good book or article/paper on digital calibration techniques?

Thanks much!
Rajdeep

Title: Re: Low offset, high speed CMOS comparator
Post by raja.cedt on Sep 19^th, 2009, 11:49pm

hi,
i will check for a good reference for calibration. The main principle is to inject current at the comparator output till offset voltage at the input is zero.

for ref you can see 3rd problem in the following examhttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee240_s09/Exams/final_s08.pdf

thanks,
Rajasekhar.

Title: Re: Low offset, high speed CMOS comparator
Post by thechopper on Sep 20^th, 2009, 8:19am

raja.cedt wrote on Sep 17^th, 2009, 8:55pm:

Calibration is certainly another option, but

1) Offset drifts (over temp) will NOT be compensated for, and that might be a problem depending on the application.
2) If done periodically, is then somehow like autozeroing the comparator in a digital rather than in an analog way, and as I pointed out before, might imply some noise performance degradation which might be important in this ckt design.

Regards
Tosei

Title: Re: Low offset, high speed CMOS comparator
Post by raja.cedt on Sep 20^th, 2009, 8:40pm

hi Tosei ,
you are correct about one time cal...but how periodic cal will cause niose problems?

Thanks,
Rajasekhar.

Title: Re: Low offset, high speed CMOS comparator
Post by thechopper on Sep 21^st, 2009, 6:02pm

Hi Rajasekhar,

That will mainly depend on the bandwith of the noise sources: if your calibration frequency is slower than 2*BWn (noise bandwith) you will start aliasing some noise into the baseband, and therefore degrading the comparator performance.

Regards
Tosei

Title: Re: Low offset, high speed CMOS comparator
Post by raja.cedt on Sep 21^st, 2009, 10:53pm

hi tosie,
thanks for updating, but what i feel you can't avoid white noise folding.

Thanks,
Rajasekhar.

Title: Re: Low offset, high speed CMOS comparator
Post by thechopper on Sep 22^nd, 2009, 7:14pm

raja.cedt wrote on Sep 21^st, 2009, 10:53pm:

hi tosie,
thanks for updating, but what i feel you can't avoid white noise folding.

Thanks,
Rajasekhar.

Most probably....but you´ll do if you chop it instead of autozeroing it.

Regards
Tosei