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Design >> Mixed-Signal Design >> Cyclic ADC
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Message started by veerendra on Sep 20^th, 2009, 11:46pm

Title: Cyclic ADC
Post by veerendra on Sep 20^th, 2009, 11:46pm

Is it possible to design 10bit 4MSPS cyclic ADC with 0.5mW Power onsumption in 90nm with 1v supply?.

Title: Re: Cyclic ADC
Post by vivkr on Sep 21^st, 2009, 11:27pm

veerendra wrote on Sep 20^th, 2009, 11:46pm:

Is it possible to design 10bit 4MSPS cyclic ADC with 0.5mW Power onsumption in 90nm with 1v supply?.

That is a very strange question. Do you want to design a 10b ADC or do you want only a cyclic ADC? It could also be SAR for instance.

Anyway, as to whether something is possible or not depends entirely on the ingenuity of the designer, but taking into account the figure of merit requirements, in this case

FOM = Power/(2^ENOB*Fs), where I liberally assume ENOB = N = 10 bits, we come to 122 fJ/step. That is aggressive but considering that you are aiming for a 10 b ADC which is on the lower end of resolution and your ENOB probably can be as bad as 9.5 or even 9 bits, I would say it is doable.

By the way, there are a few 10 b ADCs that would meet those FOM requirements (look through the high-speed ADC sections at ISSCC), although they aim for much higher speeds. My advice would be to use a SAR ADC, with some redundancy in it. Check out the paper by Kuttner at ISSCC (I think it was 2001 or 2002).

Regards,

Vivek

Title: Re: Cyclic ADC
Post by RobG on Sep 24^th, 2009, 8:26pm

veerendra wrote on Sep 20^th, 2009, 11:46pm:

Is it possible to design 10bit 4MSPS cyclic ADC with 0.5mW Power onsumption in 90nm with 1v supply?.

Like Vivek said, your are pushing the limits. A SAR or maybe a pipeline, but not a cyclic. Cyclic aren't a very power efficient ADC topology.

rg

Title: Re: Cyclic ADC
Post by vivkr on Sep 24^th, 2009, 10:41pm

RobG wrote on Sep 24^th, 2009, 8:26pm:

veerendra wrote on Sep 20^th, 2009, 11:46pm:

Is it possible to design 10bit 4MSPS cyclic ADC with 0.5mW Power onsumption in 90nm with 1v supply?.

Like Vivek said, your are pushing the limits. A SAR or maybe a pipeline, but not a cyclic. Cyclic aren't a very power efficient ADC topology.

rg

Hi Rob,

Cyclic and pipeline are essentially similar, although I would not agree with your claim that a cyclic ADC is less power-efficient than a pipeline. Rather, the two are inherently equally efficient, but work better in different cases - the pipeline for higher speed and the cyclic for lower. It is for the designer to decide which of the two is better for a given application, considering that the cyclic of course needs to run approx. Mx faster than an M-stage pipeline and is a little harder to scale in cap size (but easier if you want to scale conversion step times).

Although the SAR also needs to do a full Nx conversion, one can relax the design requirements considerably by employing Kuttner's scheme, and scaling of the individual bit conversion cycles is also possible.

Regards,

Vivek

Title: Re: Cyclic ADC
Post by RobG on Sep 30^th, 2009, 12:44pm

vivkr wrote on Sep 24^th, 2009, 10:41pm:

I believe the pipeline wins because you can scale the power consumption of the "M" MDACs in a pipeline, but in a cyclic (aka algorithmic) you just have one opamp doing the work at "M" times the sampling rate. In addition, low freq sampling is the realm of SARs and oversampling ADCs. The FOMs of SARs have been crushing anything else out there for moderate resolution.

I could be missing something... the only advantage to cyclic seems to be size.

rg

Title: Re: Cyclic ADC
Post by vivkr on Oct 1^st, 2009, 1:45am

Hi Rob,

While it is true that SARs have been steamrolling the competition at moderate rates, there are certain advantages of the cyclic ADC as well. Mind you, it is not that I am a fan of cyclic but the following points weigh in its favor:

1. You don't need to build a full N-bit DAC like in SAR. This usually presents a huge load. There are ways around that too but generally, the cyclic does this the same way as a pipeline. Of course, the cyclic/pipeline caps are larger due more kTC noise.

2. While the conversion time per stage in a pipeline is fixed at Ts, the cyclic can operate with a tapered conversion step (you should be familiar with the work done by Gil-cho and Mingyu at OSU), i.e. MSB residues get more time to do their job than LSB residues. Consider also that it is far far easier to adjust residue generation times than it is to scale pipeline stages (as in a pipelined ADC) due to the considerable design and layout effort which goes with that (Design cost is also a parameter).

3. Although there is no fundamental restriction on it, the SAR algo is going to be binary search or close to it. The cyclic frees you from this requirement by allowing arbitrary choice of gain which may allow some level of cycle-cycle scaling as well in terms of power consumption/capbank size etc. which may require limited overhead in design.

4. The cyclic does have a size advantage in most cases as you point out although I am not sure if it can compete with the SAR on size, since there is an opamp sitting there, and atleast for moderate resolution (< 10 b), the SAR ought to be smaller.

Finally, the designer needs to see which type of ADC is the best match for the requirements.

Vivek

Title: Re: Cyclic ADC
Post by RobG on Oct 1^st, 2009, 5:39am

That was a great summary. I hadn't thought of using a tapered conversion step as I was thinking their work was more about calibration. Now you have my mind gears spinning.