The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> post simulation problems with ultrasim https://designers-guide.org/forum/YaBB.pl?num=1253524395 Message started by renzhangqiang on Sep 21st, 2009, 2:13am

Title: post simulation problems with ultrasim Post by renzhangqiang on Sep 21st, 2009, 2:13am we designed our chip with TSMC 0.18um lib, the post netlist is not hierarchy,so i use ultrasim to tradeoff the speed and accuracy the problem is: this mos model is binning model(scalable),there are 20 sub-models in every mos type, nch.0 , nch.1 , nch.2 .... for nch (digital nchannal transistor). my usim_opt set up is as fellow usim_opt sim_mode=s speed=2 @nch33 usim_opt sim_mode=s speed=2 @pch33 usim_opt sim_mode=df @nch usim_opt sim_mode=df @pch but the log file shows that there is no spice & df mos transistors, all of the transistors are marked by type "a" (default ?) but when i set up like fellow: usim_opt sim_mode=da usim_opt sim_mode=s speed=2 @nch33 usim_opt sim_mode=s speed=2 @pch33 usim_opt sim_mode=df @nch usim_opt sim_mode=df @pch all of the transistors are marked as "da" , the simulator recongnise mos type only through globle announcement？ but when i change a SMIC tech lib, which is not a binning model file, there was no errors... need your help! THANK YOU! :)

The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved.