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Design Languages >> Verilog-AMS >> Verilog-A Syntax (head scratching dilema)
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Message started by eddie on Sep 22^nd, 2009, 3:06am

Title: Verilog-A Syntax (head scratching dilema)
Post by eddie on Sep 22^nd, 2009, 3:06am

Hi.
New to Verilog-A hence having some problems.
I get syntax errors on this code but helpfully it doesn't tell me what the problem is.
Here is the code:

// VerilogA for SPAD_Models, Rspad, veriloga //

`define V1 -0.000;
`define V2 -9.000;
`define V3 -9.170; //Voltage Points [user entered]
`define V4 -9.250;
`define V5 -9.320;
`define V6 -9.360;
`define V7 -9.400;

`define I1 0.000;
`define I2 3.49E-9;
`define I3 1.67E-8; //Current Points [user entered]
`define I4 6.62E-8;
`define I5 2.70E-7;
`define I6 6.62E-7;
`define I7 1.39E-6;
`include "disciplines.vams"

module Rspad(anode, cathode);

inout anode, cathode;
electrical anode, cathode;

real v, r; //define variables used below

real RA, RB, RC, RD, RE, RF;
RA = (`V2 - `V1) / (`I2 - `I1);
RB = (`V3 - `V2) / (`I3 - `I2);
RC = (`V4 - `V3) / (`I4 - `I3);
RD = (`V5 - `V4) / (`I5 - `I4);
RE = (`V6 - `V5) / (`I6 - `I5);
RF = (`V7 - `V6) / (`I7 - `I6);

analog begin
v = V(anode, cathode); //get voltage over component

if (v < `V2)
begin //conditional assignment of r
r = RA; //voltage dependant
end

else if (v < `V3) 22
begin
r = RB;
end

else if (v < `V4)
begin
r = RC;
end

else if (v < `V5)
begin
r = RD;
end

else if (v < `V6)
begin
r = RE;
end

else
begin
r = RF;
end

V(anode, cathode) = r*I(anode, cathode); //calculate voltage

end //end analog
endmodule

I get the following syntax error: Line 58: "RA = <<--? (`V2 - `V1) / (`I2 - `I1);"
The problem is mainly that I'm new to this language.
Cheers.
Ed

Title: Re: Verilog-A Syntax (head scratching dilema)
Post by Geoffrey_Coram on Sep 22^nd, 2009, 5:18am

You don't want semicolons at the end of all your `defines. At present, you end up with

RA = <<--? (-9.000; - -0.000;) / (3.49E-9; - 0.000;);

I'm also thinking you need to put parentheses around the V's (`V1) because of the double minus sign.

Title: Re: Verilog-A Syntax (head scratching dilema)
Post by eddie on Sep 22^nd, 2009, 5:58am

Thanks.
I removed the `define semicolons and changed those lines to:
RA = ( (`V2) - (`V1) ) / ( (`I2) - (`I1) );
as well as the if statements and still get exactly the same syntax error. Doesn't the <<--? in the error message mean that its before that line?
Thanks.
Ed

Title: Re: Verilog-A Syntax (head scratching dilema)
Post by Ken Kundert on Sep 22^nd, 2009, 8:06am

You need to move your assignments statements into the analog block.

Alternatively, you might try converting the assignment statements into declarations:

Code:

real RA = (`V2 - `V1) / (`I2 - `I1);
real RB = (`V3 - `V2) / (`I3 - `I2);
real RC = (`V4 - `V3) / (`I4 - `I3);
real RD = (`V5 - `V4) / (`I5 - `I4);
real RE = (`V6 - `V5) / (`I6 - `I5);
real RF = (`V7 - `V6) / (`I7 - `I6);

This is allowed with some simulators.

-Ken

Title: Re: Verilog-A Syntax (head scratching dilema)
Post by eddie on Sep 22^nd, 2009, 8:42am

Thanks.
That sorted it. I'm not amazing at debugging, especially when the problem isn't spelling or general syntax. Always difficult when you work through tutorials etc but non seem to deal with the exact problem here.
Thanks.
Ed