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Design Languages >> Verilog-AMS >> Do Verilog-A and Verilog-AMS solve analog processes differently?
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Message started by engelbrl on Sep 24^th, 2009, 11:11am

Title: Do Verilog-A and Verilog-AMS solve analog processes differently?
Post by engelbrl on Sep 24^th, 2009, 11:11am

I have two questions:
1) My understanding of how the Verilog-A/AMS analog process works is that the continuous-time kernel freezes "node" and "branch" values at every simulation time point and solves the set of differential or algebraic equations simultaneously in the analog process block. I believe the solution method can be specified as forward-Euler or trapezoidal, etc..., and that it is actually being run in the Spectre tool. Is this correct? How does one specify the solution method to use, and what is the default?

2) I began doing magnetics modeling in Verilog-A and have successfully created and run several models for spin-valves and toggle-MRAM. Now I have moved my models into Verilog-AMS in order that they may be used more easily with systemverilog. But without changing the stimulus or parameters of the system, the simulation in Verilog-AMS behaves quite differently from the simulation in Verilog-A. In fact, in Verilog-AMS I can not find a reasonable set of parameter values and stimulus to give me the proper system response that I am able to find in Verilog-A. This puzzles me greatly - Is the solution method for AMS so different? Is there a systematic way to translate a model's parameter values, etc, between the Verilog-A and AMS simulators?

Thanks,
Linda

Title: Re: Do Verilog-A and Verilog-AMS solve analog processes differently?
Post by Riad KACED on Sep 25^th, 2009, 12:59pm

Hi Linda,

Verilog-A is directly solved by Spectre. verilog-AMS is solved by the AMS engine. Any analog statements in your AMS are trated by the Ananlog Solver. The only difference I'm aware of is that verilog-A in AMS Cell Based netlisting is not run using the C-compiled flow, but rather solved by the AMS engine. This would have an impact on performance only, noy on functionality as far as I'm aware.

I do not know any translator that dumps verilog-AMS off a veriolg-A source. In fact, many verilog-A statements have to be updated to be compatible with verilog-AMS. To lean more about it, you may need to look at the 'Updating Verilog-A Modules' chapter in cadence's Verilog-AMS Language Reference manual.

Better way to get you some more efficient help if may be for you to post your verilog-A and verilog-AMS modules. I won't be the best man to llok at those files as I'm only beginning there. Many other people might help though ...

Cheers,
Riad.

Title: Re: Do Verilog-A and Verilog-AMS solve analog processes differently?
Post by Geoffrey_Coram on Sep 29^th, 2009, 10:49am

Riad KACED wrote on Sep 25^th, 2009, 12:59pm:

In fact, many verilog-A statements have to be updated to be compatible with verilog-AMS.

That's an odd statement, since Verilog-A is an official subset of Verilog-AMS. I think the updates are from an older version of Verilog-A (1.0?) to the current syntax.

Title: Re: Do Verilog-A and Verilog-AMS solve analog processes differently?
Post by Riad KACED on Oct 1^st, 2009, 9:17am

Hi Geoffrey,

You are right, Verilog-A is a subset of the Verilog-AMS.
I think I did phrase my statement is a rather confusing way. To be more precise, I would say:
"The Verilog®-A language is a subset of Verilog-AMS, but some of the language elements in that subset have changed since Verilog-A was released by itself. As a consequence, you might need to revise your Verilog-Amodules before using them as Verilog-AMSmodules. The following table highlights the differences."
That's exactly what you can read from the 'Updating Verilog-A Modules' chapter in cadence's Verilog-AMS Language Reference manual.

Cheers,
Riad.