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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> About supply voltage for RF and analog circuit of wifi with 65nm or 90nm https://designers-guide.org/forum/YaBB.pl?num=1254291820 Message started by easyads on Sep 29th, 2009, 11:23pm |
Title: About supply voltage for RF and analog circuit of wifi with 65nm or 90nm Post by easyads on Sep 29th, 2009, 11:23pm Hi Tsmc cmos65nm or 90nm provide three types of mos transistors: 1.2V, 1.8V and 3.3V. I am not deciede which type transistor should be used for RF and analog circuit of wifi. For 1.2V, the power consumption is the lowest and the design is the most difficult. For 3.3V, power consumption is the largest and design may be easiest. Many large companies such as marvel,atheros, broadcom, realtek, and csr have provide wifi chip with 65nm or 90nm cmos process. I want to know which type transistors(1.2V, 18V or 3.3V) are adopted for RF and analog circuit? Could you please give me your opinion or experience about supply voltage for RF and analog circuit for wifi under 65nm or 90nm cmos process? Thanks |
Title: Re: About supply voltage for RF and analog circuit of wifi with 65nm or 90nm Post by raja.cedt on Sep 29th, 2009, 11:51pm hi, i think for analog design always chose max voltage to get good SNR, swing.....But you can't say higher voltage leads to higher power dissipation because at higher voltage level you will get desired gain and bandwidth for lesser current ..probably the case what you have explained is digital there power dissipation is depends on the V*V. Thanks, rajasekhar. |
Title: Re: About supply voltage for RF and analog circuit of wifi with 65nm or 90nm Post by cczhang on Sep 30th, 2009, 12:34am easyads wrote on Sep 29th, 2009, 11:23pm:
hi, I don't know have think about the flicker noise about the MOSFET. in my opinion, the 1.8v 3.3v mos in 65nm/90nm process, the thickness of gate oxide will be much higher. and so the flicker noise. in the rf analog design it is bad. so i don't think you can get good performance by large vdd. cczhang |
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