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Design Languages >> Verilog-AMS >> Driver's behavior w/t or w/o dead time...
https://designers-guide.org/forum/YaBB.pl?num=1254380528

Message started by sand_dolphin2 on Oct 1^st, 2009, 12:02am

Title: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 1^st, 2009, 12:02am

Hi!!
This is the first time to write questions in this forum. :-[

I have one question of Verilog-AMS behavior of bellow case. :-?

Verilog-AMS(DUT)
// P-ch(High Side Gate) + N-ch(Low Side Gate) Driver

logic HG, LG;

analog begin
if (~HG)
V(VSW) <+ 4.5;
else if (LG)
V(VSW) <+ 0;
end

testbench-caseA(correct behavior) :)
//testcase a) w/o dead time

initial begin
HG = 1'b1;
LG = 1'b0;

#100;
forever begin
HG = 1'b0;
#640 HG = 1'b1;
LG = 1'b1;
#640 LG = 1'b0;
//#10;
end

testbench-caseB(incorrect behavior) :-/

initial begin
HG = 1'b1;
LG = 1'b0;

#105;
forever begin
HG = 1'b0;
#630 HG = 1'b1;
#10 LG = 1'b1;
#630 LG = 1'b0;
#10;
end

plz let me know somebody, :(
why does driver have incorrect behavior w/t dead time(both gate off:testbench-caseB) ?

How to design driver which have correct behavior even though w/t dead time(testbench-caseB)?

I'll wait some comments from somebody...
ciao :)

Title: Re: Driver's behavior w/t or w/o dead time...
Post by boe on Oct 2^nd, 2009, 9:07am

sand_dolphin2 wrote on Oct 1^st, 2009, 12:02am:

...
why does driver have incorrect behavior w/t dead time(both gate off:testbench-caseB) ?

How to design driver which have correct behavior even though w/t dead time
...(testbench-caseB)?

The DUT does not specify an output voltage for LG=0 & HG=1, so the node is hi-Z.
What behavior do you expect for this case?
BOE

Title: Re: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 4^th, 2009, 4:18pm

boe wrote on Oct 2^nd, 2009, 9:07am:

sand_dolphin2 wrote on Oct 1^st, 2009, 12:02am:

...
why does driver have incorrect behavior w/t dead time(both gate off:testbench-caseB) ?

How to design driver which have correct behavior even though w/t dead time
...(testbench-caseB)?

The DUT does not specify an output voltage for LG=0 & HG=1, so the node is hi-Z.
What behavior do you expect for this case?
BOE

Thanks for your kindly reply. ;)

so, My expect behavior in caseB is hi-Z cuz both gates(HG,LG) are off.

I don't know well about Verilog-AMS behavior,

but i guess in case of other statement which is not defined ,
the node will be not driven(hi-Z). :-?

anyway , even if HG or LG is on, v(VSW) does not have correct valuee..... Why... :'(

plz give some comments to solve this....
I'll wait for your and somebody's kindly reply!! :)
　
ciao :-)

Title: Re: Driver's behavior w/t or w/o dead time...
Post by boe on Oct 5^th, 2009, 8:34am

sand_dolphin2 wrote on Oct 4^th, 2009, 4:18pm:

...
so, My expect behavior in caseB is hi-Z cuz both gates(HG,LG) are off.
...
but i guess in case of other statement which is not defined ,
the node will be not driven(hi-Z). :-?

anyway , even if HG or LG is on, v(VSW) does not have correct valuee.....

The problem is that the analog solver does not notice some of the digital events because the step size is too large. You need to use edge sensitive code in DUT (switch).

Code:

analog
@(negedge HG) <statement>
end

Note that <statement> is executed only at falling edge of HG (for rising edge use posedge). However this statement should ensure analog simulator notices events.
Further, I suggest you use a transition filter to smooth out analog transitions.
BOE

Title: Re: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 5^th, 2009, 7:46pm

boe wrote on Oct 5^th, 2009, 8:34am:

sand_dolphin2 wrote on Oct 4^th, 2009, 4:18pm:

The problem is that the analog solver does not notice some of the digital events because the step size is too large. You need to use edge sensitive code in DUT (switch).

Code:

analog
@(negedge HG) <statement>
end

Thanks for your reply.
This driver should drive High at ~HG and Low at LG. and there is no case of both Gates on. and original ams have problem only both off case.

i rebuild to make ams file bellow

analog begin
@(negedge HG or posedge LG)
begin
if (~HG)
V(VSW) <+ 4.5;
else if (LG)
V(VSW) <+ 0;
end
end

but, this design drive constant value only fall/rise edge timing of HG/LG.
V(VSW)'s results is same error behavior even if testbench-caseA like as testbench-caseB . :'(

Plz give some comments!! help me.... :(

Title: Re: Driver's behavior w/t or w/o dead time...
Post by boe on Oct 7^th, 2009, 8:55am

I'd use code like
Code:

analog begin
@(posedge HG or negedge HG or posedge LG or negedge LG) begin
if (~HG & ~LG)
begin vvsw = Vhigh; res = Ron; end
else if (HG & LG)
begin vvsw = Vlow; res = Ron; end
else if (~HG & LG)
begin vvsw = Vx; res = Rx; end
else
res = Roff;
end
V(VSW) <+ transition(vvsw, ...) + transition(res, ...) * I(VSW);
end

BOE

Title: Re: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 7^th, 2009, 9:52pm

Hi boe!

boe wrote on Oct 7^th, 2009, 8:55am:

I'd use code like
Code:

BOE

Thank you for your cooperation in always :)

In this code,

　real vvsw,res;
　parameter Vhigh = 4.5;
　parameter Vlow = 0.0;
　parameter Vx = -10;
　parameter Ron = 100m;
　parameter Roff = 10M;
　parameter Rx = 1;//not occur cuz w/t deadtime

a) V(VSW) <+ transition(vvsw, ...);
　　 or
V(VSW) <+ vvsw;

b) V(VSW) <+ transition(vvsw, ...) + transition(res, ...) * I(VSW);

case a) is having a good behavior(expected)
case b) is not well. this behavior is like as first problem.

I wonder that resister should be modeled both HG and LG...
but your way is good way to keep energy of Kirchhoff's laws.

I want to make this model behave as logical function only,
so i should make this model as case a)
a) V(VSW) <+ transition(vvsw, ...);

Thank's a lots of your kinds ;)

ciao
See you soon!! bye for now

Title: Re: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 12^th, 2009, 4:23pm

Hi boe and somebody !!

In this post of first step

logic HG,LG;
electrical VSW_temp;

analog begin
if (~HG) // Polarity Inverted (consistency for transister model)
V(VSW_temp) <+ 4.5;
else if (LG)
V(VSW_temp) <+ 0;

//V(VSW) <+ V(VSW_temp);//CaseA
V(VSW) <+ transition(V(VSW_temp),0,trise,tfall);//CaseB
end

w/t transition function CaseB is running well,but w/o transition function CaseA is not good. :-?

What doese make this differ behavior btw w/t and w/o ?
Should we use transition function to act analog solver by trigger of digital solver ? :(

I'll wait for your comments!! ;)
ciao :)

Title: Re: Driver's behavior w/t or w/o dead time...
Post by boe on Oct 15^th, 2009, 9:34am

sand_dolphin2 wrote on Oct 12^th, 2009, 4:23pm:

...
w/t transition function CaseB is running well,but w/o transition function CaseA is not good. :-?

What doese make this differ behavior btw w/t and w/o ?
Should we use transition function to act analog solver by trigger of digital solver ? :(
...

Steps in a signal (of type electrical) are usually bad for convergence, so using a transition filter (which ensures that the signal V(VSW) is differentiable) improves convergence and simulation speed. I also suggest you use a real variable for VSW_temp: this should simulate faster (electrical signals have a lot of overhead).
Hope this helps.
BOE

[Edit:]PS: If you use a transition filter, you need the resistor term to model HiZ.

Title: Re: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 15^th, 2009, 5:07pm

Hi boe!!
Thank you for your cooperation in always!! :)

boe wrote on Oct 15^th, 2009, 9:34am:

sand_dolphin2 wrote on Oct 12^th, 2009, 4:23pm:

In this case,
there is no need to add transition "filter",
the reason for using transition function is to solve this first step problem.

So, your suggestion of should use not electrical but real
at the solving first step problem,
w/o transition function V(VSW)<+V(VSW_temp); can't treat real.
the nanosim compiler output error code.
then i treat VSW_temp as electrical.

Why should i use transition function for solving this first step problem?
Plz help me... :-[

See you soon,
ciao ;)

Title: Re: Driver's behavior w/t or w/o dead time...
Post by boe on Oct 16^th, 2009, 4:18am

sand_dolphin2 wrote on Oct 15^th, 2009, 5:07pm:

...
In this case,
there is no need to add transition "filter",
the reason for using transition function is to solve this first step problem.

So, your suggestion of should use not electrical but real
at the solving first step problem,
w/o transition function V(VSW)<+V(VSW_temp); can't treat real.
the nanosim compiler output error code.
then i treat VSW_temp as electrical.

A voltage step across a capacitance requires a (momentaneous) infinite current spike (Dirac pulse), which usually causes problems with the simulator. Even without capacitance at node VSW, simulator convergence should be better with transition "function" (called "transition filter" in the LRM).
The transition filter helps in two ways: 1. It ensures finite first derivative of the voltage and 2. it provides the simulator with information for step size control (rise/fall time).
Therefore you should use
Code:

V(VSW) <+ transition(...);

For efficiency reasons you should use a real variable in your if statement. Because (some) simulators consider every assignment to the variable in the transition filter an event (even if the value does not change), you should put the if statement in an analog event control (@) statement as I suggested in reply #5 (http://www.designers-guide.org/Forum/YaBB.pl?num=1254380528#5)
BOE

[Added:]The other purpose of using an analog event control statement is to ensure that no events are lost (by adding analog time points at transitions).

Title: Re: Driver's behavior w/t or w/o dead time...
Post by sand_dolphin2 on Oct 19^th, 2009, 12:50am

boe wrote on Oct 16^th, 2009, 4:18am:

V(VSW) <+ transition(...);

For efficiency reasons you should use a real variable in your if statement. Because (some) simulators consider every assignment to the variable in the transition filter an event (even if the value does not change), you should put the if statement in an analog event control (@) statement as I suggested in reply #5 (http://www.designers-guide.org/Forum/YaBB.pl?num=1254380528#5)
BOE
[Added:]The other purpose of using an analog event control statement is to ensure that no events are lost (by adding analog time points at transitions).

Thank you for your cooperation in always :)
　
I had solved by your kindly advice.
This should be closed, i think.
　how about anybody?　 :(
　if so,please add message or questions ;)

See you soon BOE!
ciao :)