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Design >> Analog Design >> pipelined ADC stages integration
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Message started by balu on Oct 11^th, 2009, 6:53am

Title: pipelined ADC stages integration
Post by balu on Oct 11^th, 2009, 6:53am

I am designing a 12 bit 80 MHz pipelined ADC which consists of 6 stages of 3 bit each. I have completed one 3 bit stage. now iam integrated all six stages, but iam not able to get eaxct residue after 2nd stage to pass on to third stage and so on.
can anyone please answer to my question

regards
BALU

Title: Re: pipelined ADC stages integration
Post by vivkr on Oct 12^th, 2009, 12:13am

Hi Balu,

This indicates to me that your pipeline stage is not accurate enough. Note that you will anyway never get the exact residue. The question is simply whether the resulting error is small enough to meet your spec.

Here are a few possible things I can imagine going wrong in your design:

1. Insufficient transient gain (i.e. virtual ground at opamp input not sufficiently accurate at the end of the settling phase). Note that it is largely pointless to look merely at AC simulations of DC gain and bandwidth. You need to also look at settling of the entire MDAC under correct loading and operating conditions.

2. Offset due to charge-injection. If you are using a good switching scheme and have only fixed signal-independent charge-injection, then you probably don't care. Otherwise, you need to fix those switches.

3. Capacitor mismatch. This is probably not there in your simulations anyway.

4. Comparator offset. There will likely be some systematic offset depending on your design which will move the transition points of your residue transfer curve. You may even have some hysteresis.

The list can be extended arbitrarily but you can concentrate on these major factors, particularly 1.

Regards,

Vivek